Patents by Inventor Kwok Keung Paul Ho

Kwok Keung Paul Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150003056
    Abstract: The present invention provides an enhanced light out-coupling device for extraction of light radiation from a light source. The enhanced light out-coupling device comprises a grid having a plurality of channels, a reflective material layer coated on the grid, and a high refractive index fluid layer. In addition, the grid can be filled with phosphor particles for light converting. The device of the presently claimed invention is able to effectively avoid the scattering problem generated from the sapphire substrate and phosphor particles, as well as reduce light adsorption by the array of grid during the light extraction, leading to better image quality.
    Type: Application
    Filed: May 7, 2014
    Publication date: January 1, 2015
    Applicant: Nano and Advanced Materials Institute Limited
    Inventors: Tsang Ming Michael CHOI, Yuen Yan Gena TSANG, Kwok Keung Paul HO
  • Patent number: 6877517
    Abstract: A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: April 12, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Xue Chun Dai
  • Patent number: 6790374
    Abstract: A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: September 14, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Xuechun Dai
  • Publication number: 20040110389
    Abstract: A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species.
    Type: Application
    Filed: October 27, 2003
    Publication date: June 10, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Kwok Keung Paul Ho, Xue Chun Dai
  • Patent number: 6705512
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 16, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Publication number: 20020155693
    Abstract: A new method of fabricating self-aligned, anti-via interconnects has been achieved. A semiconductor substrate is provided. A metal layer is deposited overlying the semiconductor substrate. The metal layer may comprise a composite stack of two metal layers. The metal layers may additionally be separated by an etch stopping layer. An anti-reflective coating layer is deposited overlying the metal layer. The metal layer is etched through to form connective lines. The metal layer is then etched partially through to form vias. The partial etching through may be accomplished by timed etching or by use of the optional etching stop layer. A dielectric layer is deposited overlying the vias, the connective lines and the semiconductor substrate. The dielectric layer may comprise a low-k material. The dielectric layer is polished down to complete the self-aligned, anti-via interconnects in the manufacture of the integrated circuit device.
    Type: Application
    Filed: April 23, 2001
    Publication date: October 24, 2002
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sangki Hong, Subhash Gupta, Kwok Keung Paul Ho
  • Publication number: 20020100794
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Application
    Filed: March 15, 2002
    Publication date: August 1, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6417088
    Abstract: A method of forming a conductive cap layer over a metal bonding pad comprises the following steps. A semiconductor structure is provided having an exposed, recessed metal bonding pad within a layer opening. The layer has an upper surface. The exposed metal bonding pad is treated with a solution containing soluble metal ions to form a conductive cap over the metal bonding pad. The conductive cap layer is comprised of the solution metal and has a predetermined thickness. An external bonding element may then be bonded to the conductive cap, forming an electrical connection with the metal bonding pad.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: July 9, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6415973
    Abstract: A method of bonding a bonding element to a metal bonding pad, comprising the following steps. A semiconductor structure having an exposed metal bonding pad within a passivation layer opening is provided. The bonding pad has an upper surface. A bonding element is positioned to contact the bonding pad upper surface. A bonding solution is applied within the passivation layer opening, covering the bonding pad and a portion of the bonding element. The structure is annealed by heating said bonding element to selectively solidify the bonding solution proximate said contact of said bonding element to said bonding pad, bonding the bonding element to the bonding pad.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: July 9, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Mei Sheng Zhou, Yakub Aliyu, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6387859
    Abstract: A cleaner composition for removing from within a microelectronic fabrication a copper containing residue layer in the presence of a copper containing conductor layer, and a method for stripping from within a microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer. The cleaner composition comprises: (1) a hydroxyl amine material; (2) an ammonium fluoride material; and (3) a benzotriazole (BTA) material. The cleaner composition contemplates the method for stripping from within the microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: May 14, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Kwok Keung Paul Ho
  • Patent number: 6378759
    Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: April 30, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6123088
    Abstract: A cleaner composition for removing from within a microelectronic fabrication a copper containing residue layer in the presence of a copper containing conductor layer, and a method for stripping from within a microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer. The cleaner composition comprises: (1) a hydroxyl amine material; (2) an ammonium fluoride material; and (3) a benzotriazole (BTA) material. The cleaner composition contemplates the method for stripping from within the microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: September 26, 2000
    Assignee: Chartered Semiconducotor Manufacturing Ltd.
    Inventor: Kwok Keung Paul Ho
  • Patent number: 6114243
    Abstract: A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: September 5, 2000
    Assignee: Chartered Semiconductor Manufacturing Ltd
    Inventors: Subhash Gupta, Kwok Keung Paul Ho, Mei-Sheng Zhou, Simon Chool