Patents by Inventor Kwon-Young Choi
Kwon-Young Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10153490Abstract: The present disclosure provides a novel composite transition metal oxide-based precursor, a preparing method thereof, and a cathode active material for a secondary battery prepared from the precursor. In the present disclosure, it is possible to enhance productivity and economic efficiency due to a high reaction yield during the synthesis of a cathode active material and to enhance the initial discharge capacity and lifespan characteristics of a secondary battery including a cathode active material by using an oxide-based precursor having a high oxygen fraction instead of a hydroxide-based precursor used as a precursor of a cathode active material in the related art.Type: GrantFiled: November 21, 2016Date of Patent: December 11, 2018Assignee: LG Chem, Ltd.Inventors: Seo Hee Ju, Kwon Young Choi, Sung Ho Ban, Jun Ho Eom
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Publication number: 20170317349Abstract: The present disclosure provides a novel composite transition metal oxide-based precursor, a preparing method thereof, and a cathode active material for a secondary battery prepared from the precursor. In the present disclosure, it is possible to enhance productivity and economic efficiency due to a high reaction yield during the synthesis of a cathode active material and to enhance the initial discharge capacity and lifespan characteristics of a secondary battery including a cathode active material by using an oxide-based precursor having a high oxygen fraction instead of a hydroxide-based precursor used as a precursor of a cathode active material in the related art.Type: ApplicationFiled: November 21, 2016Publication date: November 2, 2017Applicant: LG Chem, Ltd.Inventors: Seo Hee JU, Kwon Young CHOI, Sung Ho BAN, Jun Ho EOM
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Publication number: 20150249268Abstract: The present disclosure relates to a lithium secondary battery. The lithium secondary battery includes a cathode, an anode, a separator interposed between the cathode and the anode, and a non-aqueous electrolyte solution, the non-aqueous electrolyte solution includes an ionizable lithium salt and an organic solution, and includes, based on 100 parts by weight of the non-aqueous electrolyte solution, (a) 1 part by weight to 10 parts by weight of a compound containing a vinylene group or vinyl group, and (b) 0.1 parts by weight to 10 parts by weight of a dinitrile-based ether compound of a particular structure, and the cathode includes a mixture of a first cathode active material LixCoO2(0.5<x<1.3) and a second cathode active material LixMyO2(M is Ni1-a-bMnaCob(0.05?a?0.4, 0.1?b?0.4, 0.4?1-a-b?0.7) in which x+y=2 and 0.95?x?1.05. The lithium secondary battery has a high capacity, and remarkably suppresses a swelling phenomenon at high temperature of the battery.Type: ApplicationFiled: September 30, 2014Publication date: September 3, 2015Applicant: LG Chem, Ltd.Inventors: Yeon-Suk Hong, Jae-Seung Oh, Byoung-Bae Lee, Sang-Hyun Lee, Kwon-Young Choi, Dong-Su Kim, Hyo-Jin Lee
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Patent number: 8703345Abstract: Disclosed is an electrolyte. The electrolyte includes an amide compound and an ionizable lithium salt. The amide compound has a specific structure in which an amine group is substituted with at least one alkoxyalkyl group and at least one halogen atom is present. The electrolyte has good thermal and chemical stability, a low resistance and a high ionic conductivity. In addition, the electrolyte has a high upper limit of electrochemical window due to its improved oxidation stability. Therefore, the electrolyte can be useful for the fabrication of an electrochemical device. Further disclosed is an electrochemical device including the electrolyte.Type: GrantFiled: September 23, 2011Date of Patent: April 22, 2014Assignee: LG Chem, Ltd.Inventors: Byoung-Bae Lee, Jae-Seung Oh, Sang-Hyun Lee, Kwon-Young Choi, Dong-Su Kim, Yeon-Suk Hong, Hyo-Jin Lee
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Publication number: 20120077091Abstract: Disclosed is an electrolyte. The electrolyte includes an amide compound and an ionizable lithium salt. The amide compound has a specific structure in which an amine group is substituted with at least one alkoxyalkyl group and at least one halogen atom is present. The electrolyte has good thermal and chemical stability, a low resistance and a high ionic conductivity. In addition, the electrolyte has a high upper limit of electrochemical window due to its improved oxidation stability. Therefore, the electrolyte can be useful for the fabrication of an electrochemical device. Further disclosed is an electrochemical device including the electrolyte.Type: ApplicationFiled: September 23, 2011Publication date: March 29, 2012Applicant: LG CHEM, LTD.Inventors: Byoung-Bae LEE, Jae-Seung OH, Sang-Hyun LEE, Kwon-Young CHOI, Dong-Su KIM, Yeon-Suk HONG, Hyo-Jin LEE
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Patent number: 8068188Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: June 18, 2008Date of Patent: November 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20110033904Abstract: Disclosed herein is a method for preparing ortho-dihydroxyisoflavones using a biotransformation system. More specifically, disclosed is a method for preparing ortho-dihydroxyisoflavones, which comprises biotransforming daidzein or genistein by actinomycete microorganisms, particularly Streptomyces avermitilis, Nocardia farcinica or Streptomyces lincolnesis, in order to efficiently prepare ortho-dihydroxyisoflavones having an excellent antioxidant function and a whitening effect.Type: ApplicationFiled: April 25, 2008Publication date: February 10, 2011Inventors: Jun Seong Park, Hye Yoon Park, Ho Sik Rho, Duck Hee Kim, Ih Seop Chang, Byung Gee Kim, Chang Hyun Roh, Su Hyun Seo, Kwon Young Choi, June Hyung Kim, Min-Ho Cha, Prasad Pandey Bishnu
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Patent number: 7883942Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.Type: GrantFiled: October 19, 2007Date of Patent: February 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Gee Baek, Kwon-Young Choi, Young-Joon Rhee, Bong-Joo Kang, Seung-Taek Lim, Hyang-Shik Kong, Won-Joo Kim
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Patent number: 7742118Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: March 23, 2007Date of Patent: June 22, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20100096176Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.Type: ApplicationFiled: December 22, 2009Publication date: April 22, 2010Inventors: Seung-Taek LIM, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-Kyu Song
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Patent number: 7659625Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.Type: GrantFiled: December 12, 2008Date of Patent: February 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Taek Lim, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-Kyu Song
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Patent number: 7566906Abstract: A thin film transistor array panel is provided, which includes a substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer; a plurality of ohmic contacts formed on the semiconductor layer; source and drain electrodes formed on the ohmic contacts; a passivation layer formed on the source and the drain electrodes and having a first contact hole exposing a portion of the drain electrode and an opening exposing a first portion of the semiconductor layer and having edges that coincide with edges of the source and the drain electrodes; and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole.Type: GrantFiled: December 17, 2007Date of Patent: July 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Wook Park, Bum-Ki Baek, Jeong-Young Lee, Kwon-Young Choi, Sang-Ki Kwak, San-Jin Jeon
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Patent number: 7550329Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.Type: GrantFiled: May 13, 2008Date of Patent: June 23, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sahng-Ik Jun, Jae-Hong Jeon, Kwon-Young Choi, Jeong-Young Lee
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Publication number: 20090096105Abstract: In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads.Type: ApplicationFiled: December 12, 2008Publication date: April 16, 2009Inventors: Seung-Taek LIM, Mun-Pyo Hong, Nam-Seok Roh, Young-Joo Song, Sang-Ki Kwak, Kwon-Young Choi, Keun-Kyu Song
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Patent number: 7459323Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconType: GrantFiled: August 30, 2006Date of Patent: December 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Wook Park, Sang-Jin Jeon, Jung-Joon Park, Jeong-Young Lee, Bum-Ki Baek, Se-Hwan Yu, Sang-Ki Kwak, Han-Ju Lee, Kwon-Young Choi
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Publication number: 20080252806Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: ApplicationFiled: June 18, 2008Publication date: October 16, 2008Inventors: Jun-Hyung SOUK, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20080210943Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.Type: ApplicationFiled: May 13, 2008Publication date: September 4, 2008Inventors: Sahng-Ik Jun, Jae-Hong Jeon, Kwon-Young Choi, Jeong-Young Lee
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Patent number: 7408200Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line formed on the substrate and intersecting the first signal line; a thin film transistor including a gate electrode connected to the first signal line and having an edge substantially parallel to the first signal line, a source electrode connected to the second signal line, and a drain electrode overlapping the edge of the gate electrode; and a pixel electrode connected to the drain electrode.Type: GrantFiled: December 18, 2006Date of Patent: August 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sahng-Ik Jun, Jae-Hong Jeon, Kwon-Young Choi, Jeong-Young Lee
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Patent number: 7403240Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.Type: GrantFiled: April 27, 2007Date of Patent: July 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hyung Souk, Jeong-Young Lee, Jong-Soo Yoon, Kwon-Young Choi, Bum-Ki Baek
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Publication number: 20080093600Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.Type: ApplicationFiled: December 17, 2007Publication date: April 24, 2008Inventors: Min-Wook PARK, Bum-Ki Baek, Jeong-Young Lee, Kwon-Young Choi, Sang-Ki Kwak, Sang-Jin Jeon