Patents by Inventor Kwong Hon Wong

Kwong Hon Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8896090
    Abstract: A fuse, a method of making the fuse and a circuit containing the fuse. The fuse includes an electrically conductive and conformal liner on sidewalls and the bottom of a trench; a copper layer on the conformal liner, a first thickness of the copper layer over the bottom of the trench in a lower portion of the trench greater than a second thickness of the copper layer over the sidewalls of the trench in an abutting upper portion of the trench; and a dielectric material on the copper layer in the trench, the dielectric material filling remaining space in the upper portion of said trench.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nicholas R. Hogle, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 8895371
    Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Dechao Guo, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong
  • Publication number: 20140332862
    Abstract: Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.
    Type: Application
    Filed: August 15, 2013
    Publication date: November 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong
  • Publication number: 20140332860
    Abstract: Methods and systems for forming stacked transistors. Such methods include forming a lower channel layer on a substrate; forming a pair of vertically aligned gate regions over the lower channel layer; forming a pair of vertically aligned source regions and a pair of vertically aligned drain regions on the lower channel material, each pair separated by an insulator; forming an upper channel material over the source regions, drain regions, and gate regions; and providing electrical access to the source, drain, and gate regions.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong
  • Publication number: 20140319650
    Abstract: An method and structure of forming an electronic fuse. The method including forming a first metal line and a second metal line in a first interconnect level, wherein the first metal line is electrically insulated form the second metal line, and forming a via in a second interconnect level above the first interconnect level, the via electrically and physically connecting the first metal line with the second metal line. The via may create a sub-lithographic contact with the underlying metal line, thus increasing current density and probability of failure at a specific location.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Jason Coyner, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Publication number: 20140312412
    Abstract: Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses, wherein the source and drain contacts extend above the channel layer.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DECHAO GUO, SHU-JEN HAN, YU LU, KEITH KWONG HON WONG
  • Publication number: 20140312413
    Abstract: Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer.
    Type: Application
    Filed: August 16, 2013
    Publication date: October 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Yu Lu, Keith Kwong Hon Wong
  • Patent number: 8866214
    Abstract: A transistor structure is formed to include a substrate and, overlying the substrate, a source; a drain; and a channel disposed vertically between the source and the drain. The channel is coupled to a gate conductor that surrounds the channel via a layer of gate dielectric material that surrounds the channel. The gate conductor is composed of a first electrically conductive material having a first work function that surrounds a first portion of a length of the channel and a second electrically conductive material having a second work function that surrounds a second portion of the length of the channel. A method to fabricate the transistor structure is also disclosed. The transistor structure can be characterized as being a vertical field effect transistor having an asymmetric gate.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Patent number: 8853788
    Abstract: In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Publication number: 20140291760
    Abstract: In a method of fabricating a FET semiconductor device, a FET structure with a gate channel and dummy gate is formed on a layer of substrate. The gate channel includes one or more FINs, and spacer layers that line the sides of the gate channel and abut the layer of substrate. The dummy gate is removed and the height of the gate channel is reduced to substantially near that of a top surface of one or more FINs. A layer of high-k material is deposited into the gate channel. A layer of first metal is then deposited that fills the gate channel and covers, at least in part, the layer of high-k material. Excess material is removed from the layers of high-k material and first metal to create a surface. A layer of second metal is selectively deposited onto the surface to form a continued gate conductor.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 8815734
    Abstract: A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 8809176
    Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
  • Patent number: 8803328
    Abstract: Randomized coded arrays and method of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yunsheng Song, Keith Kwong Hon Wong, Yongchun Xin, Zhijian Yang
  • Publication number: 20140217504
    Abstract: FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.
    Type: Application
    Filed: April 22, 2014
    Publication date: August 7, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eduard A. CARTIER, Brian J. GREENE, Dechao GUO, Gan WANG, Yanfeng WANG, Keith Kwong Hon WONG
  • Publication number: 20140217481
    Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.
    Type: Application
    Filed: February 3, 2013
    Publication date: August 7, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J. Jaeger, Yu Lu, Keith Kwong Hon Wong
  • Patent number: 8796854
    Abstract: A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong, Haining S. Yang
  • Patent number: 8796773
    Abstract: In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Keith Kwong Hon Wong
  • Publication number: 20140210041
    Abstract: An electronic fuse structure including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the dielectric layer and the seed layer causing the seed layer to reflow and fill the first via opening, the second via opening, and partially filling the trench opening to form a fuse line, a first via, and a second via. The structure further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Publication number: 20140206190
    Abstract: Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed, causing the semiconductor substrate to react with the metal layer forming a metal-rich silicide layer on the semiconductor substrate. Embodiments may also include forming a low-oxygen capping layer above the metal layer prior to annealing the semiconductor substrate to protect the metal layer from oxidation. The low-oxygen capping layer may, for example, be made of titanium nitride containing less than 20 parts per million of oxygen. Embodiments may further include forming a silicide layer using the above process in a contact hole above a source/drain region of a field-effect transistor, and forming a metal contact above the silicide layer.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: BAOZHEN LI, YUN Y. WANG, KEITH KWONG HON WONG, CHIH-CHAO YANG
  • Publication number: 20140203448
    Abstract: Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Yunsheng Song, Keith Kwong Hon Wong, Yongchun Xin, Zhijian Yang