Patents by Inventor Kwong Wong

Kwong Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7747828
    Abstract: A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: June 29, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Yunsheng Wang, Casey Springer, Tak Kwong Wong, Bill Beane
  • Patent number: 7688105
    Abstract: An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: March 30, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventor: Tak Kwong Wong
  • Publication number: 20100071568
    Abstract: An integrated cleaning and cutting device includes a case, a cover sealed the case, a basket received in the case, and a basket shelter mounted on the basket. A plurality of palings is formed on the basket. A drive mechanism is accumulated in the cover for driving the basket to rotate in the case. A cutting mechanism is fitted in the cover for cutting salad material. The cutting mechanism includes a blanking hole communicating with the basket in the case. The salad material is cleaned in the basket by the rotating of the basket in the case. On the other hand, the salad material can be cut and stored in the device, in which the basket and the cutting mechanism are equipped. Since the device has multiple functions such as cleaning, cutting and storage, it is utilitarian in use.
    Type: Application
    Filed: September 16, 2009
    Publication date: March 25, 2010
    Inventor: Yan Kwong Wong
  • Publication number: 20100031073
    Abstract: Systems and methods are disclosed for managing power consumption in electronic devices. In certain embodiments, an integrated circuit for managing power consumption in an electronic device includes an input/output (I/O) interface, a first circuit block coupled to the I/O interface, and an interface circuit coupled between the I/O interface and the first circuit block, the interface circuit configured to provide a defined logic state to the first circuit block or a second circuit block external to the integrated circuit if one of the first circuit block or the second circuit block is powered down. By providing a defined logic state to the first circuit block or the second circuit block when one of the first circuit block or the second circuit block is powered down, power consumption of the electronic device may be reduced.
    Type: Application
    Filed: August 1, 2008
    Publication date: February 4, 2010
    Inventors: Tzong-Kwang Henry Yeh, Tak Kwong Wong
  • Publication number: 20100007373
    Abstract: An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).
    Type: Application
    Filed: July 9, 2008
    Publication date: January 14, 2010
    Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Tak Kwong Wong
  • Patent number: 7647535
    Abstract: A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds TCYCLE, and (2) such that the signal delay between the second and third registers is less than TCYCLE minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within TCYCLE.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: January 12, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventor: Tak Kwong Wong
  • Patent number: 7571300
    Abstract: A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: August 4, 2009
    Assignee: Integrated Device Technologies, Inc.
    Inventor: Tak Kwong Wong
  • Publication number: 20090104463
    Abstract: Compositions and methods for depositing gold alloys are disclosed. The compositions include certain dithiocarboxylic acids, salts and esters thereof and mercapto group containing compounds which provide bright gold alloy deposits with uniform color.
    Type: Application
    Filed: December 16, 2008
    Publication date: April 23, 2009
    Inventors: Andre Egli, Wing Kwong Wong, Raymund W. M. Kwok, Jochen Heber
  • Patent number: 7465385
    Abstract: Compositions and methods for depositing gold alloys are disclosed. The compositions include certain dithiocarboxylic acids, salts and esters thereof and mercapto group containing compounds which provide bright gold alloy deposits with uniform color.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: December 16, 2008
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: André Egli, Wing Kwong Wong, Raymund W. M. Kwok, Jochen Heber
  • Publication number: 20080246913
    Abstract: A detachable eyewear is designed for eyeglasses. The detachable eyewear is designed similar to an eyeglass frame without temples, which comprises lenses, a rim and two tension adjustment stoppers with hooks each positioned to the respective extensions at the two ends of the rim and each of the tension adjustment stopper is connected by a nylon string, wherein said detachable eyewear is attached in front of the primary eyeglasses. With the flexibility and elasticity endowed with nylon strings, the tension adjustment stoppers with hooks at each end can be opened although they are fixed onto the two ends of the rim. By way of the elastic force, said detachable eyewear adapted to be attached and secured by said hooks of the tension adjustment stoppers to said eyeglasses, either clip-on or clip-off the studs. The detachable eyewear is specially designed which can be in a number of prescriptions. This detachable eyewear is handled easily and attached stably.
    Type: Application
    Filed: April 3, 2007
    Publication date: October 9, 2008
    Inventor: Wan Kwong Wong
  • Patent number: 7430958
    Abstract: A double blade peeling device for vegetable and fruit comprises a handle attached to a vegetable and fruit retaining member and a body of screw, the handle can drive internal gears to rotate, so as to make the retaining member and the body of screw to rotate as well. The body of screw, which is provided with two screw threads, drives upper and lower blade carriers to move upward and downward oppositely, such that the blades mounted on the upper and lower blade carriers move downward and upward respectively, contact the rotating food frictionally, and peel vegetable or fruit from upside and underside simultaneously. When two blade carriers move to the intermediate position to complete the peeling action, the two blade carriers open through wedge in blade carrier devices, two blades leave the surface of food, the lower blade carrier devices disengage with the body of screw. The body of screw drives upper blade carrier device to press the lower blade carrier device to move downward unceasingly.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: October 7, 2008
    Inventor: Yan Kwong Wong
  • Publication number: 20080168256
    Abstract: A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 10, 2008
    Applicant: Integrated Device Technology, Inc.
    Inventor: Tak Kwong Wong
  • Publication number: 20080143383
    Abstract: A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds TCYCLE, and (2) such that the signal delay between the second and third registers is less than TCYCLE minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within TCYCLE.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Applicant: Integrated Device Technology, Inc.
    Inventor: Tak Kwong Wong
  • Publication number: 20080136443
    Abstract: A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 12, 2008
    Applicant: Integrated Device Technology, Inc.
    Inventor: Tak Kwong Wong
  • Publication number: 20080045039
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Application
    Filed: October 17, 2007
    Publication date: February 21, 2008
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS, INC.
    Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
  • Publication number: 20080036007
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Application
    Filed: October 19, 2007
    Publication date: February 14, 2008
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS, INC.
    Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
  • Publication number: 20080014663
    Abstract: A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
    Type: Application
    Filed: July 12, 2007
    Publication date: January 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis Hsu, Timothy Dalton, Lawrence Clevenger, Carl Radens, Kwong Wong, Chih-Chao Yang
  • Publication number: 20070277682
    Abstract: The multi-function juicer is a tool used for meat grinding and juice extraction. By changing the blade and screw bolt inside, it can serve the double purpose of either meat grinding or juice extraction. By repetitively rotating the handle, the screw bolt and the blade will rotate, too. This will drive the meat to pass through the pedal blade to smash into smaller ground meat, or drive the fruit to pass through the rotating blade and screw bolt to extract juice. The wetness of the pulp can be adjusted by controlling the wetness control unit. There is no need for extra processes to separate the juice from pulp, or to control the wetness of the pulp. It provides a convenient way to use one simple juicer to extract juice from different fruits. The other special point of this invention is that it has a vacuum disk on the bottom. Before meat grinding or juice extraction, the user only needs to rotate the handle inside the body.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 6, 2007
    Inventor: Yan Kwong Wong
  • Patent number: D581725
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: December 2, 2008
    Inventor: Yan Kwong Wong
  • Patent number: D618517
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: June 29, 2010
    Inventor: Yan Kwong Wong