Abstract: A flip-chip package structure includes a flexible interconnection structure, at least one chip, a stiffener layer, and an isolating layer. The flexible interconnection structure having a plurality of bumps on a top surface, a plurality of contact terminals on a bottom surface, and an inner circuit connected to the bumps and the contact terminals. The chip and the stiffener layer are mounted on the top surface of the flexible interconnection structure, and the isolating layer is attached on the bottom surface. The isolating layer includes a plurality of openings that respectively expose the contact terminals of the flexible interconnection structure.

Abstract: A structure of a chip package and a process thereof are provided. The process of the chip package makes use of the TFT-LCD panel or IC process to increase the circuit layout density for high electrical performance. First, a multi-layer interconnection structure with pads of high layout density and thin fine circuits is formed on a base substrate with a large-area and high co-planarity surface, wherein the base substrate is made of quartz or glass or ceramics. Then, a chip is located on the top surface of the multi-layer interconnection structure by flip-chip or wire-bonding technology. Then, a substrate or a heat sink is attached on the top surface of the multi-layer interconnection structure for being a stiffener and providing mechanical support. Finally, the base substrate is removed and contacts are attached on the bottom surface of the multi-layer interconnection structure.

Abstract: A structure of a chip package and a process thereof are provided. The process of the chip package makes use of the TFT-LCD panel or IC process to increase the circuit layout density for high electrical performance. First, a multi-layer interconnection structure with pads of high layout density and thin fine circuits is formed on a base substrate with a large-area and high co-planarity surface, wherein the base substrate is made of quartz or glass or ceramics. Then, a chip is located on the top surface of the multi-layer interconnection structure by flip-chip or wire-bonding technology. Then, a substrate or a heat sink is attached on the top surface of the multi-layer interconnection structure for being a stiffener and providing mechanical support. Finally, the base substrate is removed and contacts are attached on the bottom surface of the multi-layer interconnection structure.

Abstract: A fabrication process and a structure of a laminated capacitor. A substrate is provided, and multiple electrode and dielectric layers, formed using high-speed physical metal deposition and dielectric material coating, respectively, are alternately stacked to form a laminated capacitor structure. In addition, a pair of terminal electrodes is formed on two sides of the electrode layers. The terminal electrodes are electrically connected to the electrode layers. A surface metallic layer is formed on the exposed surface of the terminal electrodes to prevent the surface from being oxidized. Thereby, the adhesion between the electrode layers and the dielectric layers is improved. The thickness uniformity ratio of the dielectric layers can be maintained at about ∈±10%. The relative displacement between two neighboring electrode layers can be smaller than about 100 microns to approach the standard capacitance required by the laminated capacitor.