CHIP PACKAGING STRUCTURE
A flip-chip package structure includes a flexible interconnection structure, at least one chip, a stiffener layer, and an isolating layer. The flexible interconnection structure having a plurality of bumps on a top surface, a plurality of contact terminals on a bottom surface, and an inner circuit connected to the bumps and the contact terminals. The chip and the stiffener layer are mounted on the top surface of the flexible interconnection structure, and the isolating layer is attached on the bottom surface. The isolating layer includes a plurality of openings that respectively expose the contact terminals of the flexible interconnection structure.
This application is a continuation-in-part of a prior application Ser. No. 10/249,060, filed Mar. 13, 2003. The prior application Ser. No. 10/249,060 claims the priority benefit of Taiwan application serial no. 91132740, filed on Nov. 7, 2002.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates generally to a chip packaging structure and a packaging process thereof. More particularly, the invention provides a chip packaging structure and a chip packaging process to increase the circuit layout density for high electrical performance.
2. Description of the Related Art
A flip chip interconnection structure usually consists of mounting a chip on a carrier substrate via a plurality of conductive bumps that electrically and mechanically connect the die pads of the chip to bump pads of the carrier substrate. Such an interconnection structure is particularly suitable for chip packages with a high pin count, and has the advantages of providing smaller surface areas and shorter electrical paths. Presently, two types of flip chip interconnection structures known in the art are a flip chip ball grid array (FC/BGA) package and a flip chip pin grid array (FC/PGA) package.
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An underfill compound 160 is further formed in the gap between the active surface 132 of the chip 130 and the top surface 112 of the substrate 110 to seal and protect the conductive bumps 140 by sharing thermal strains due to a thermal mismatch between the substrate 110 and the chip 130.
As the dimensional size of the chip package is reduced, the surface area of the chip and the pitch between the bump pads of the chip become increasingly smaller. In other words, the density of the die pads becomes higher. To adequately accommodate the density of the die pads of the chip, the substrate also has to be provided with a high density of bump pads and a finer circuit layout.
The known FC/BGA or FC/PGA package currently uses a substrate made of ceramic or organic based materials. It should be remarked that the organic substrate is more common. Due to a substantial thermal expansion of the organic material, the trace width and trace pitch currently obtainable inside the substrate are limited to be above 25 μm. The bumps disposed on the chip also have a height at lest 100 μm. Furthermore, due to the nature of its material, a maximal size of the blank (before cutting) of the organic substrate is limited to 610 mm×610 mm. The above technical limitations of the prior art are not satisfactory in view of current demands.
SUMMARY OF THE INVENTIONAn aspect of the invention is therefore to provide a chip packaging structure that increases the circuit layout density of the multi-layer interconnection structure for higher electrical performance.
Another aspect of the invention is to provide chip packaging structure that reduces the production cost.
To accomplish the above and other objectives, a chip packaging structure of the invention comprises a multi-layered interconnection structure, a chip, a stiffener layer, and an isolating layer. The multi-layered interconnection structure has a plurality of bumps on a top surface and a plurality of contact terminals on a bottom surface, and internally includes inner electrical circuits connected to the bumps and the contact terminals. The multi-layered interconnection structure is a flexible structure which is built-up on a base substrate. The chip is mounted on the top surface of the multi-layered interconnection structure in a manner to be electrically connected to the bumps according to a flip chip type. The stiffener layer has a cavity, and is attached on the top surface of the multi-layered interconnection structure with the cavity receiving the chip therein. The isolating layer is attached on the bottom surface of the multi-layered interconnection structure, and includes a plurality of openings that respectively expose a plurality of contact terminals on the bottom surface of the multi-layered interconnection structure.
According to an embodiment of the invention, the stiffener layer comprises a stiffener substrate and a heat sink. The stiffener substrate includes a hole, and the heat sink is attached on the stiffener substrate in a manner to cover the hole.
According to another embodiment of the invention, the stiffener layer is a heat sink.
According to a preferred embodiment of the invention, the base substrate is made of quartz or glass or ceramics, and a fabrication process of a thin film transistor-liquid crystal display (TFT-LCD) panel or a fabrication process of an integrated circuit (IC) is used to form the multi-layered interconnection structure over the base substrate. The obtained multi-layered interconnection structure thereby has bump pads and inner circuit layout with a higher density.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
The following detailed description of the embodiments and examples of the present invention with reference to the accompanying drawings is only illustrative and not limiting. Furthermore, wherever possible in the description, the same reference symbols will refer to similar elements and parts unless otherwise illustrated in the drawings.
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According to a preferred embodiment, a processing technique used in the fabrication of thin film transistor/liquid crystal display (TFT-LCD) panels is implemented to form the multi-layered interconnection structure. The obtained width and pitch of both the conductive traces 208 within the structure 206 are between about 1 μm and 50 μm and, more particularly, in the order of microns (even smaller than 1 μm). Therefore, compared with the usually known organic substrate 110 of
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The connection members 240 are preferably distributed in grid array on the bottom surface 206b of the structure 206, so that the formed chip package is either a ball grid array or pin grid array package depending on whether the connection members 240 are solder balls or connection pins.
As described above, the chip packaging process of the invention therefore economically uses a stiffener substrate that, associated with a heat sink, reinforce the mechanical strength of the package structure and further promote heat dissipation through the heat sink. Alternatively, a single heat sink provided with a cavity may be substituted for the above association of a stiffener substrate and a heat sink as described in the following second embodiment of the invention.
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A sealing compound 346 is filled in the gaps between the chip 314 and the structure 306 and the gaps between the chip 314 and the inner sides of the cavity 344 to prevent a popcorn effect.
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The above embodiments describe a packaging structure that principally comprises a single chip. However, more than one chip may be also similarly included in the packaging structure as described below.
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As described above, the invention therefore provides a chip packaging comprising a flexible interconnection structure, at least one chip, a stiffener layer and an isolating layer. The flexible interconnection structure having a plurality of bumps on a top surface, a plurality of contact terminals on a bottom surface, and the inner electrical circuits electrically connected to the bumps and the contact terminals. The chip is connected to the bumps of the flexible interconnection structure by a flip-chip type.
The chip package is fabricated through the following steps: providing the base substrate; forming the isolating layer on the base substrate; forming the multi-layered interconnection structure on the isolating layer; mounting the chip on the top surface of the multi-layered interconnection structure; attaching the stiffener layer on the top surface of the multi-layered interconnection structure; removing the base substrate; and forming the openings of the isolating layer. The openings of the isolating layer could be formed after removing the base substrate or before forming the multi-layered interconnection structure on the isolating layer. The advantages implemented in the invention are:
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- 1. The flexible interconnection structure with a high density of bump pads and a finer inner circuit layout (trace pitch and trace width.
- 2. The specific flexible interconnection structure used in the invention can advantageously accommodate one or more chips having a high density of bump pads.
- 3. The flexible interconnection structure allows an easier control of the electrical impedance of the conductive traces.
- 4. The contact terminals on the bottom surface of the flexible interconnection structure are the solder balls or the conductive pins.
- 5. Furthermore, the base substrate can have a larger surface area, typically larger than 610 mm×610 mm. More chip packages can be therefore fabricated from a single base substrate, which decreases the fabrication cost.
It should be apparent to those skilled in the art that other structures that are obtained from various modifications and variations of different parts of the above-described structures of the invention would be possible without departing from the scope and spirit of the invention as illustrated herein. Therefore, the above description of embodiments and examples only illustrates specific ways of making and performing the invention that, consequently, should cover variations and modifications thereof, provided they fall within the inventive concepts as defined in the following claims.
Claims
1. A chip package structure, comprising:
- a flexible interconnection structure, having a top surface and an opposite bottom surface, the flexible interconnection structure including inner electrical circuits that are electrically connected to a plurality of bumps on the top surface of the flexible interconnection structure and a plurality of contact terminals located on the bottom surface of the flexible interconnection structure, wherein the bumps have a height not larger than 50 μm;
- at least one chip, mounted on the top surface of the flexible interconnection structure and electrically connected to the bumps;
- a stiffener layer, attached on the top surface of the flexible interconnection structure; and
- an isolating layer, attached to the bottom surface of the flexible interconnection structure, the isolating layer including a plurality of openings that respectively expose the contact terminals on the bottom surface of the multilayered interconnection structure, wherein the isolating layer and the flexible interconnection structure are sequentially formed on a base substrate before the chip and the stiffener layer are attached on the top surface of the flexible interconnection structure.
2. The chip package structure of claim 1, wherein the chip is mounted on the top surface of the flexible interconnection structure by a flip-chip type.
3. The chip package structure of claim 1, wherein the stiffener layer includes a stiffener substrate with a hole and a heat sink attached on the stiffener substrate in a manner to cover the hole, wherein the structure of the stiffener substrate and the heat sink results in the cavity of the stiffener layer.
4. The chip package structure of claim 3, wherein the stiffener substrate includes inner circuits that are electrically connected to the inner electrical circuits of the flexible interconnection structure.
5. The chip package structure of claim 3, wherein the stiffener substrate further includes at least one passive component that is embedded therein.
6. The chip package structure of claim 3, wherein the stiffener substrate further includes at least one passive component that is mounted on a surface thereof.
7. The chip package structure of claim 1, wherein the stiffener layer has a cavity that receives the chip therein.
8. The chip package structure of claim 7, wherein the stiffener layer is a heat sink.
9. The chip package structure of claim 1, further comprising at least a passive component formed inside the flexible interconnection structure and electrically connected to the inner electrical circuits.
10. The chip package structure of claim 1, wherein the bumps are selected from the group consisting of Au, Cu, Ni and Sn.
11. The chip package structure of claim 10 further comprises a soldering material disposed between the bumps of the flexible interconnection structure and the chip, such that the bumps of the flexible interconnection structure and the chip are electrically connected through a thermal-pressing process.
12. The chip package structure of claim 1, wherein the bumps are made of a soldering material.
13. The chip package structure of claim 1, wherein the base substrate is selected from one of the glass, quartz and ceramics.
14. The chip package structure of claim 1, wherein the contact terminals are a plurality of solder balls.
15. The chip package structure of claim 1, wherein the contact terminals are a plurality of conductive pins.
16. The chip package structure of claim 1, wherein the flexible interconnection structure is formed through a build-up process on the base substrate.
17. The chip package structure of claim 1, wherein the base substrate is removed after the chip and the stiffener layer are attached on the top surface of the flexible interconnection structure.
18. A method for fabricating the chip package structure of claim 17, comprising the following steps:
- providing the base substrate;
- forming the isolating layer on the base substrate;
- forming the multi-layered interconnection structure on the isolating layer;
- mounting the chip on the top surface of the multi-layered interconnection structure;
- attaching the stiffener layer on the top surface of the multi-layered interconnection structure;
- removing the base substrate; and
- forming the openings of the isolating layer.
19. The method claim 18, wherein the openings of the isolating layer are formed after removing the base substrate.
20. The method of claim 18, wherein the openings of the isolating layer are formed before forming the multi-layered interconnection structure on the isolating layer.
Type: Application
Filed: Jun 30, 2005
Publication Date: Oct 20, 2005
Inventors: Kwun-Yo Ho (Taipei Hsien), Moriss Kung (Taipei Hsien)
Application Number: 11/160,592