Abstract: A semiconductor device includes a memory chip having a memory cell array including a plurality of memory blocks, wherein the memory chip includes a plurality of test pads for testing operations of the memory blocks, and an interface chip including a penetrating electrode and a plurality of interface circuit blocks, wherein at least one of the interface circuit blocks is electrically connected to at least one of the memory blocks via the penetrating electrode, and wherein the interface chip includes a plurality of bonding pads for interfacing between the interface circuit blocks and an external device.

Abstract: A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may further include a column select gate configured to control transfer of data from a memory cell to the local input/output line and the control circuit may be configured to disable transfer of data via the column select gate responsive to the global input/output line sense amplifier enable signal.

Abstract: Provided are an apparatus which provides termination with respect to signals transmitted through a bus line, and a memory system using the apparatus which can prevent the number of sockets from increasing and a continuity module from being used. The termination providing apparatus includes a termination resistor having one end connected to a termination voltage, and is configured in a concave form to be mounted on an upper end of a memory module or in a convex form to be mounted in a socket. The memory system employs the termination providing apparatus, that is, a concave termination cap mounted on an upper end of a memory module, a convex termination cap mounted in a socket, and a top bus extension component mounted on upper ends of two memory modules and forming signal routing between the two memory modules.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.

Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

Abstract: A signal transmission apparatus may transmit and receive a differential signal using transmission lines. The apparatus may include a transmitter and a receiver. The transmitter may transmit a mixed signal obtained by mixing the differential signal with a single ended signal. The receiver may restore the differential signal and the single ended signal from the mixed signal. An edge of the single ended signal may have a phase difference of about 90° with an edge of the differential signal. The signal transmission apparatus and method may transmit two signals through a single channel to reduce a circuit area.

Abstract: A semiconductor integrated circuit and method for burn-in-testing are provided that uniformly apply stress to elements of the semiconductor integrated circuit in a burn-in test mode, even when packaged. The semiconductor integrated circuit may include a transmission control unit that transmits an operation signal in a normal operating mode and blocks the operation signal in the test mode; and a test control unit that sequentially outputs a first signal and a second signal to an input/output (I/O) circuit in the test mode.

Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

Abstract: A dynamic semiconductor memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs. A mode setting portion receives a mode setting code applied from an external portion to generate a power saving mode control signal for a power saving mode of operation responsive to a mode setting command. An address control portion decodes an address applied from an external portion or a refresh address to select one of the plurality of the word lines during a normal mode operation. The address control portion also selects a predetermined number of bits of the address during a power saving mode of operation. The semiconductor memory device, therefore extends the refresh cycle while reducing the refresh time resulting in a lower power consumption.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A memory module device for use in a high frequency operation provides for ease in synchronization. In one example, the memory module includes integrated buffers, each having first and second data ports connected to respective data buses in a point-to-point configuration, such that data input through either data port of the first and second data ports is transferred to the memory device and is simultaneously output through the other data port of the first and second data ports. The integrated buffers each further include first and second command address ports connected to respective command address buses in a point-to-point configuration, such that a command address signal input through either port of the first and second command address ports is transferred to the memory device and simultaneously output through the other command address port of the first and second command address ports.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: Disclosed herein is a circuit and method for generating a boost element drive signal in a semiconductor memory device with a mode register set signal. The boost element drive signal generation circuit includes a preliminary drive signal generation unit and a level shifter. The preliminary drive signal generation unit generates a preliminary drive signal in response to a group of mode setting signals. The mode setting signal group is provided from a mode register set. The level shifter generates the boost element drive signal in response to the preliminary drive signal. The pull-up voltage of the boost element drive signal is level-shifted relative to a pull-up voltage of the preliminary drive signal. According to the boost element drive signal generation circuit of the present invention, the activation instant of a boost element drive signal is controlled by a mode setting signal group. Therefore, the boost element drive signal is activated after a boost voltage is stabilized.

Abstract: A memory system, memory module and memory device are described. The memory system includes a plurality of the memory modules connected in a series configuration on a first signal path. The first signal path and a second signal path carry memory control and data signals between the memory modules and a memory controller. The memory controller transmits and receives the control signals and data signals on the first and second signal paths. The first and second signal paths are connected together such that the memory modules are connected in a ring configuration. The control signals and data signals travel in opposite directions on the first and second signal paths. The first and second signal paths are shared by both the data signals and the control signals. The memory modules include multi-functional ports, each of which can receive both the control signals and the data signals and output the signals onto the connected signal paths.

Abstract: A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may further include a column select gate configured to control transfer of data from a memory cell to the local input/output line and the control circuit may be configured to disable transfer of data via the column select gate responsive to the global input/output line sense amplifier enable signal.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Abstract: A semiconductor memory device that includes a memory cell connected to a wordline and a wordline voltage generator. The wordline voltage generator supplies a first negative voltage to the wordline in a standby state and supplies a second negative voltage that is lower with respect to ground than the first negative voltage to the wordline in a refresh operation. Accordingly, a leakage current generated at a transistor of a memory cell by gate-induced drain leakage (GIDL) is suppressed to enhance the performance of a refresh operation.