Abstract: A step height between first and second elevated conductive lines that are laterally spaced apart on an integrated circuit substrate may be reduced by forming a dummy conductive line beneath the second conductive line, to further elevate the second conductive line on the integrated circuit substrate. Depth-of-focus may thereby be improved so that reliability of the conductive lines may also be improved. The second conductive line and the dummy conductive line vertically overlap by an amount that is less than one half the width of the second conductive line. Thus, the capacitance between the second conductive line and the dummy conductive line may be reduced. Undue delay therefore need not be created by introduction of the dummy conductive line.

Abstract: Disclosed is a memory device, comprising a memory controller, a clock input pin for receiving a clock signal, a first chip selection signal input pin for receiving a first chip selection signal for a row address strobe from the memory controller, a second chip selection signal input pin for receiving a second chip selection signal for a column address strobe from the memory controller, a row command input pin for receiving a row command from the memory controller, a column command input pin for receiving a column command from the memory controller, a plurality of row address input pins for receiving row addresses from the memory controller, and a plurality of column address input pins for receiving column addresses from the memory controller.

Abstract: Integrated circuit memory devices having data input and output lines in a column direction and circuits and methods for repairing faulty cells are provided. A column select line according to the present invention extends along a row direction. Data input and output lines extend along a column direction. In repairing faulty cells, the column having the faulty cells is not directly replaced by a redundancy column but rather is replaced by an adjacent column. Thus, an increase of layout area upon increase of the input and output lines can be reduced. The operational current also may be reduced. Differences in parasitic capacitance from the respective columns to global input and output lines also may be reduced. Also, the faulty cells may be repaired without lowering the speed at which data is input and output during the redundancy operation.

Abstract: Integrated circuit memory devices having data input and output lines in a column direction are provided. A column select line according to the present invention extends along a row direction. Data input and output lines extend along a column direction. Thus, an increase of layout area upon increase of the input and output lines can be reduced. The operational current also may be reduced. Differences in parasitic capacitance from the respective columns to global input and output lines also may be reduced.

Abstract: An integrated circuit memory device includes a test mode. Data is written to and read from the integrated circuit memory device in the test mode. The integrated circuit memory device includes a memory array that includes memory cells that store data. A test control circuit generates control signals that control the data read from the memory cells. A data output circuit outputs data read from the memory cells from the integrated circuit memory device in response to the test column address strobe signal. In particular, the test column address strobe signal includes a series of high to low and low to high transitions, wherein the data output circuit outputs data read from the memory cells in response to the series of high to low and low to high transitions.

Abstract: An integrated circuit memory device and method including a direct mode assigns internal data and address signals to separate pins. In particular, a plurality of first pins is assigned to the plurality of internal data signals that provide the data to the memory array in direct test mode. A plurality of second pins is assigned to the plurality of internal address signals that provide the address to the memory array in direct test mode, wherein none of the pins included in first plurality of pins are included in the second plurality of pins.

Abstract: Integrated circuit memory devices include test mode control circuits to more efficiently route test data to a fewer number of output pins during test mode operation. The memory device may include first and second memory arrays having first and second pluralities of data lines electrically coupled thereto, respectively. First and second pluralities of latch units are also provided. The first plurality of latch units are electrically coupled together in series as a first pipelined latch unit and electrically coupled in parallel to the first memory array by the first plurality of data lines. The second plurality of latch units are electrically coupled together in series as a second pipelined latch unit and electrically coupled in parallel to the second memory array by the second plurality of data lines. A preferred test mode control circuit electrically couples an output of the first pipelined latch unit to an input of the second pipelined latch unit, in response to a test mode control signal (.phi.DAE).

Abstract: Integrated circuit memory devices include a plurality of pads that receive signals from external of the memory device and a plurality of data buses, a respective one of which is operatively connected to a respective one of the plurality of pads. A plurality of multiplexers is provided, a respective one of which is operatively connected to a respective one of the pads and to each of the data buses, to write data from the data buses to the memory cell in a direct access test mode, and to write data from the respective one of the pads to the memory cell array in a normal mode. The integrated circuit memory devices also preferably include a plurality of input/output devices, a respective one of which operatively connects the respective one of the pads to the respective one of the multiplexers. The plurality of input/output devices preferably are a plurality of pipelines that store signals that are serially received from external of the memory device, and that provide the stored signals to the multiplexers.

Abstract: A high voltage generating circuit for a semiconductor memory device includes a plurality of charge pumps which are connected to a common output line and repetatively activated in sequence. Each pump operates for a predetermined on time after it is activated. In standby mode, the pumps are activated at a low frequency so that the amount of time between the activation of successive pumps is longer than the predetermined on time, and thus, each pump is deactivated before the next pump is activated. This results in only a small amount of charge being transferred to the output line during standby mode. In active mode, the pumps are activated at a higher frequency such that the on times of the individual pumps overlap and several pumps operate simultaneously. Thus, a larger amount of charge is transferred during active mode. Since the individual pumps are activated at different times, power supply noise is reduced.

Abstract: A reference voltage generating circuit has a divider circuit for decreasing a received external power-supply voltage and for providing the decreased voltage at a reference voltage output terminal. A PMOS transistor clamps the reference voltage at a predetermined voltage level, one end thereof being coupled to the reference voltage output terminal and the other end being coupled to a ground. A compensating unit adjusts the substrate voltage of the PMOS transistor to compensate for level variations of the reference voltage in response to the level variations. Thus, variations in the reference voltage caused by changes in processing variables are compensated, thereby maintaining the reference voltage at a predetermined level.

Abstract: An integrated circuit memory device includes a plurality of memory cells, a plurality of data lines, a memory cell selector, and a memory cell connector. The memory cells are arranged in a matrix of rows and columns wherein the plurality of memory cells are further grouped in banks with each bank including at least two rows of memory cells. Each of the data lines extends along one of the columns of memory cells so that each of the data lines extends along memory cells from each of the banks of memory cells. The memory cell selector includes a row decoder which selects one of the plurality of rows, a column decoder which selects one of the plurality of columns, and a bank decoder which selects one of the banks. The connector connects one of the memory cells to a respective data line in response to the memory cell selector. Accordingly, data from only one of the memory cells is provided on a respective one of the data lines at any point and time.

Abstract: A semiconductor memory device includes input/output circuitry capable of operating in sync with an externally provided I/O clock signal. A data in buffer and a data out buffer provide for serial to parallel conversion of write data and, conversely, parallel to serial conversion of read data. The data buffers can be synchronized with the external I/O clock signal thereby decoupling their operation from the internal system clock signal. This strategy improves I/O bandwidth and further provides for matching different numbers of bit lines or word sizes as between the I/O data port and the memory array itself. An internal I/O clock generator can be provided for generating I/O clock signals, again without the limitation of synchronizing to the internal system clock signal.