Abstract: A magnetic random access memory (MRAM) using a common line is described herein. An MTJ element is positioned on the common line of the MRAM. The common line connected to a source of a transistor transmits a ground level voltage for reading data and supplies a current for writing data.

Abstract: The method for manufacturing an FeRAM capacitor having an enhanced adhesive property between a dielectric layer and a bottom electrode and a grain uniformity of the dielectric layer, is employed by forming hillocks on the bottom electrode purposefully before formation of the dielectric layer. The method includes steps of: preparing an active matrix obtained by predetermined processes; forming a first bottom electrode on the active matrix; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on a top face of the bottom electrode; carrying out a first annealing process for deforming a surface of the second bottom electrode; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the third ILD; carrying out a second annealing process; and forming a top electrode on the dielectric layer.

Abstract: A method for manufacturing an FeRAM capacitor is employed to enhance an adhesive property between a dielectric layer and a first bottom electrode of iridium. The method including the steps of: preparing an active matrix including a semiconductor substrate, a transistor, a bit line, a first ILD, a second ILD and a storage node; forming a first bottom electrode on the second ILD and the storage node; forming a third ILD on exposed surfaces of the first bottom electrode and the second ILD; planarizing the third ILD till a top face of the first bottom electrode is exposed; forming a second bottom electrode on the top face of the bottom electrode; forming conductive oxides on exposed sidewalls of the first bottom electrode by carrying out an oxidation process; forming a dielectric layer on exposed surfaces of the first bottom electrodes, the second bottom electrode and the second ILD; and forming a top electrode on the dielectric layer.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.

Abstract: The present invention discloses methods for manufacturing MTJ cell of MRAM wherein the surface of a pinned magnetic layer having a crystalline structure of long range order is physically impacted with heavy ions or atom to form an amorphous layer having a crystalline structure of short range order. In accordance with the method, a metal layer for connection layer and a pinned magnetic layer are formed. A surface of the pinned magnetic layer is physically impacted with atom to form an amorphous layer. A tunneling barrier layer, a free magnetic layer and a MTJ capping layer are sequentially formed and the MTJ capping layer, the free magnetic layer, the tunneling barrier layer, amorphous layer and the pinned magnetic layer are patterned using a MTJ cell mask to form a MTJ cell.

Abstract: Magnetic random access memories (MRAM) are disclosed. The MRAM stores multi-level data by electronically coupling one diode and a plurality of resistance transfer devices, thereby improving a storage capacity and property of the device and achieving high integration thereof. The MRAM may also include a diode, a word line electrically coupled to the diode, a connection layer electrically coupled to the diode; and a plurality of connection pairs each comprising a resistance transfer device and a bit line electrically coupled to the resistance transfer device. One of the connection pairs may be formed on the connection layer, and the bit line of another connection pair may be perpendicular to the bit line of the first connection pair.

Abstract: The present invention discloses methods for manufacturing MTJ cell of MRAM wherein two annealing process with different magnitudes of applied magnetic fields are performed. In accordance with the method, the formation process of second pinned magnetic layer comprises a first annealing process and a second annealing process, wherein a magnitude of a magnetic field applied during the first annealing process being larger than that of a magnetic field applied during the second annealing process.

Abstract: A method for manufacturing a MRAM wherein a MTJ cell and a connection layer are simultaneously patterned, and an insulating film spacer and a hard mask layer are used as etching masks instead of a photoresist film to simplify the manufacturing process and to prevent generation of a metal polymer is disclosed.

Abstract: A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline).

Abstract: A magnetic random access memory (MRAM) is disclosed, which achieves high integration by forming second word lines that serve as two write lines for one pair of MRAMs. A contact plug is formed by connecting the second word line to a metal wire formed above the bit lines. As a result, the bit lines and the contact plug are used to drive the device, thereby achieving high integration of the device.

Abstract: A method for manufacturing a magnetic random access memory is disclosed. An interlayer insulating film is formed on a lower read layer, a cell region of the interlayer insulating film is etched according to a photo etching process using a cell mask, and a MTJ layer is formed on the lower read layer of the cell region and the interlayer insulating film of a peripheral circuit region. The sidewall of the interlayer insulating film is exposed, the MTJ layer is left merely in the cell region by lifting off the interlayer insulating film, and a bit line which is an upper read layer connected to the MTJ layer is formed in a succeeding process. Accordingly, an effective area of an MTJ cell is obtained and the properties and reliability of the MRAM are improved.

Abstract: A magnetic random access memory (MRAM) is disclosed, which achieves high integration by forming second word lines that serve as two write lines for one pair of MRAMs. A contact plug is formed by connecting the second word line to a metal wire formed above the bit lines. As a result, the bit lines and the contact plug are used to drive the device, thereby achieving high integration of the device.

Abstract: A magnetic random access memory (MRAM) using a common line is described herein. An MTJ element is positioned on the common line of the MRAM. The common line connected to a source of a transistor transmits a ground level voltage for reading data and supplies a current for writing data.

Abstract: The present invention provides a magnetic random access memory (MRAM) cell device with a magnetic tunnel junction capable of obtaining a sufficient sense margins. To achieve this effect, the present invention provides a magnetic random access memory (MRAM) cell device, including: a word line; a bit line; a switching unit connected to the word line and the bit line; a magnetic tunnel junction unit connected to the bit line and the switching unit in parallel.

Abstract: Magnetic random access memorys (MRAM) are disclosed. The MRAMs store multi-level data by connecting one diode and a plurality of resistance transfer devices, thereby improving a storage capacity and property of the device and achieving high integration thereof.

Abstract: A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a channel ion region by implanting impurity ions into the active region of the semiconductor substrate, forming a first conductive film pattern on a portion of the semiconductor substrate which corresponds to the channel ion region, forming a channel region having lower concentration than the channel ion region by implanting impurity ions in a different type from the ions in the channel ion region into a center portion of the channel ion region through the first conductive film pattern, forming a second conductive film pattern on the first conductive film pattern, forming an impurity region of low concentration in the semiconductor substrate with the first and second conductive film patterns as a mask, forming a sidewall spacer at both sides of the first and second conductive film patterns, and forming an impurity regi

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate insulating film on a substrate, forming semiconductor layer on the gate insulating film, selectively removing the semiconductor layer to form first and second gate electrodes, implanting ions of a first conductive type into the first gate electrode, and implanting impurity ions of a second conductive type into the second gate electrode.