Abstract: Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPAR? and PPAR? activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease.

Abstract: Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPAR? and PPAR? activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease.

Abstract: A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a DUT under the control of a DQ signal responding to a DQ enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array. The programmed logical value is captured from the DUT under the control the DQ signal. The generated logical value is compared with the captured logical value. Whether the DUT is defective is determined according to a result of the comparison. The DQ enable signal is applied to a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the field programmable gate array is applied.

Abstract: A test device includes a test unit and a voltage selection circuit. The test unit is configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad. The voltage selection circuit is configured to apply a selection voltage to a ground pad of the semiconductor device under test by selecting one of a plurality of voltages according to a test mode.

Abstract: Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPAR? and PPAR? activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease.

Abstract: Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPAR? and PPAR? activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease.

Abstract: A semiconductor device, which is mounted on a device interface board to interface an electrical measuring signal between automated test equipment (ATE) and a device under test (DUT), includes an AC test unit, a DC test unit, a first input/output (I/O) interface unit, and a second I/O interface unit. The AC test unit tests an AC characteristic of the DUT. The DC test unit provides a DC test path according to attributes of I/O terminals of the DUT. The first I/O interface unit selectively connects the AC test unit or the DC test unit to the ATE in response to a mode control signal. The second I/O interface unit selectively connects the AC test unit or the DC test unit to the DUT in response to the mode control signal.

Abstract: Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPAR? and PPAR? activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease.

Abstract: A test interface board comprises at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other. The at least one switch matrix is configured to connect a plurality of channels of an automatic test equipment (ATE) to respective pin positions corresponding to a device under test (DUT) in response to switching control signals. The plurality of channels provide test operation signals for testing the DUT. A control logic is configured to generate the switching control signals based on pin configuration information of the DUT.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A method of setting a function and a display apparatus applying the same are provided. The method of setting a function of the display apparatus includes displaying a set item list, which includes one or more set items, on a screen of the display apparatus; and in response to a set item on the set item list being selected, providing a menu for accessing one or more other set items associated with the selected set item.

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.

Abstract: A method for controlling a security channel for reducing system load by extending the use period of a security association key is provided. In this method, an upper bit initial value of an initialization vector of an encryption algorithm and a using range thereof are shared between a transmitting side and a receiving side when a security channel is created. Then, a secure association is created between a transmitting side and a receiving side by setting an association number, a next packet number which is a lower bit value of an initialization vector, and a secure association key. Afterward, a packet number is modified whenever a frame is transmitted until all of packet numbers are used. When all packet numbers are used, the upper bit value of the initialization vector changes.