Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: In a non-volatile semiconductor memory device which differentially uses a start programming voltage during a programming operation mode in order to reduce a dispersion for the number of programming loops, the programming method includes previously storing a row address that indicates at least one specific word line among a plurality of word lines; and applying a start programming voltage to the specific word line, when a row address applied in a programming operation mode coincides with the stored row address, the start programming voltage having a level that is different from a level of start programming voltage to be applied to the rest word lines except the specific word line, whereby reducing dispersion for the programming loop number and realizing a high-speed programming operation and operating efficiency.

Abstract: A high-speed Galois Counter Mode-Advanced Encryption Standard (GCM-AES) block cipher apparatus and method is provided. The apparatus can operate at a low clock frequency of 125 MHz and provide a 2 Gbps link encryption function in an Optical Line Termination (OLT) and an Optical Network Unit (ONU) of an Ethernet Passive Optical Network (EPON). 11-round block cipher of 128-bit input data is implemented using an 8-round Counter-AES (CTR-AES) block cipher module and a 3-round CTR-AES block cipher module, so that it is possible to provide a 1 Gbps link security function for an input frequency of 62.5 MHz and a 2 Gbps link security function for an input frequency of 125 MHz.

Abstract: An authentication method for link protection between an OLT and an ONU newly connected thereto in an EPON, which is implemented in a data link layer to which cryptography is applied. First, an authentication key is distributed to both the OLT and an ONU. The OLT (or ONU) generates first and second random values, generates an authentication request frame containing the random values, and transmits it to the ONU (or OLT). The ONU generates a first hash value according to a hash function using the random values contained in the request frame, and transmits an authentication response frame containing the first hash value to the OLT. The OLT compares the first hash value with a second hash value calculated by it according to the has function using the two random values and an authentication key distributed to it, and transmits an authentication result frame to the ONU.

Abstract: A non-volatile memory device according to some embodiments of the invention includes a number of memory cells and a word line voltage generator circuit. The word line voltage generator circuit generates a program voltage that is applied to the memory cells every program loop of a program cycle. The word line voltage generator circuit may generate a program voltage for one program loop that is different from a program voltage for each of the remaining program loops. Other embodiments are described and claimed.

Abstract: In a non-volatile semiconductor memory device which differentially uses a start programming voltage during a programming operation mode in order to reduce a dispersion for the number of programming loops, the programming method includes previously storing a row address that indicates at least one specific word line among a plurality of word lines; and applying a start programming voltage to the specific word line, when a row address applied in a programming operation mode coincides with the stored row address, the start programming voltage having a level that is different from a level of start programming voltage to be applied to the rest word lines except the specific word line, whereby reducing dispersion for the programming loop number and realizing a high-speed programming operation and operating efficiency.

Abstract: Embodiments of the invention provide a power-on reset function that establishes logic circuits in a memory chip at an initial stable state and a power-on read function that triggers a read operation of the memory chip. A first voltage detector output signal transitions when a power supply voltage reaches a first voltage, setting the logic circuits at the initial stable state. A second voltage detector output signal transitions when the power supply voltage reaches a second voltage, placing a latch in a set state that results in activation of a power-on read signal. A power-on read operation is carried out according to the activation of the power-on read signal. If the power supply voltage is not lowered below the first voltage, the second voltage detector output signal does not transition. Accordingly, embodiments are capable of preventing power-on read operations that are unnecessarily performed owing to power noise.

Abstract: A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.

Abstract: A flash memory device including a memory cell array block including a plurality of flash memory cells. A program verify voltage generating unit variably generates a program verify voltage that verifies flash memory cells programming. A wordline level selecting unit transfers the program verify voltage to the flash memory cells. And a page buffer, including a latch, stores flash memory cell data and resets the latch whenever the program verify voltage is lowered.

Abstract: A flash memory device including a memory cell array block including a plurality of flash memory cells. A program verify voltage generating unit variably generates a program verify voltage that verifies flash memory cells programming. A wordline level selecting unit transfers the program verify voltage to the flash memory cells. And a page buffer, including a latch, stores flash memory cell data and resets the latch whenever the program verify voltage is lowered.

Abstract: Embodiments of the invention provide a power-on reset function that establishes logic circuits in a memory chip at an initial stable state and a power-on read function that triggers a read operation of the memory chip. A first voltage detector output signal transitions when a power supply voltage reaches a first voltage, setting the logic circuits at the initial stable state. A second voltage detector output signal transitions when the power supply voltage reaches a second voltage, placing a latch in a set state that results in activation of a power-on read signal. A power-on read operation is carried out according to the activation of the power-on read signal. If the power supply voltage is not lowered below the first voltage, the second voltage detector output signal does not transition. Accordingly, embodiments are capable of preventing power-on read operations that are unnecessarily performed owing to power noise.