Abstract: Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPAR? and PPAR? activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease.

Abstract: A semiconductor device, which is mounted on a device interface board to interface an electrical measuring signal between automated test equipment (ATE) and a device under test (DUT), includes an AC test unit, a DC test unit, a first input/output (I/O) interface unit, and a second I/O interface unit. The AC test unit tests an AC characteristic of the DUT. The DC test unit provides a DC test path according to attributes of I/O terminals of the DUT. The first I/O interface unit selectively connects the AC test unit or the DC test unit to the ATE in response to a mode control signal. The second I/O interface unit selectively connects the AC test unit or the DC test unit to the DUT in response to the mode control signal.

Abstract: Provided are a novel compound having skin-whitening, anti-oxidizing and PPAR activities and a medical use thereof, and the compound has skin-whitening activities for the suppression of tyrosinase, and accordingly, is useful for use in skin-whitening pharmaceutical composition or cosmetic products; has anti-oxidant activities, and accordingly, is useful for the prevention and treatment of skin-aging; and has PPAR activities, and in particular, PPAR? and PPAR? activities, and accordingly, is useful for use in pharmaceutical compositions or health foods which are effective for the prevention and treatment of obesity, metabolic disease, or cardiovascular disease.

Abstract: A test interface board comprises at least one switch matrix including a plurality of switching elements that connect a plurality of connection nodes to each other. The at least one switch matrix is configured to connect a plurality of channels of an automatic test equipment (ATE) to respective pin positions corresponding to a device under test (DUT) in response to switching control signals. The plurality of channels provide test operation signals for testing the DUT. A control logic is configured to generate the switching control signals based on pin configuration information of the DUT.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode.

Abstract: A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.

Abstract: A method for controlling a security channel for reducing system load by extending the use period of a security association key is provided. In this method, an upper bit initial value of an initialization vector of an encryption algorithm and a using range thereof are shared between a transmitting side and a receiving side when a security channel is created. Then, a secure association is created between a transmitting side and a receiving side by setting an association number, a next packet number which is a lower bit value of an initialization vector, and a secure association key. Afterward, a packet number is modified whenever a frame is transmitted until all of packet numbers are used. When all packet numbers are used, the upper bit value of the initialization vector changes.

Abstract: A data output buffer switches it operating mode according to its operating frequency. The data output buffer includes a delay control unit, and a buffer unit. The buffer unit provides data of an internal buffer input line to an external buffer output line. The delay control unit generates a buffer enable signal corresponding to a received reference control signal. The buffer unit blocks the provision of the data to the buffer output line in response to a deactivation of the buffer enable signal. The buffer enable signal remains in an activated state when the period of the reference control signal is shorter than a reference period. The data output buffer may be included in a semiconductor memory device.

Abstract: In a non-volatile semiconductor memory device which differentially uses a start programming voltage during a programming operation mode in order to reduce a dispersion for the number of programming loops, the programming method includes previously storing a row address that indicates at least one specific word line among a plurality of word lines; and applying a start programming voltage to the specific word line, when a row address applied in a programming operation mode coincides with the stored row address, the start programming voltage having a level that is different from a level of start programming voltage to be applied to the rest word lines except the specific word line, whereby reducing dispersion for the programming loop number and realizing a high-speed programming operation and operating efficiency.

Abstract: An authentication method for link protection between an OLT and an ONU newly connected thereto in an EPON, which is implemented in a data link layer to which cryptography is applied. First, an authentication key is distributed to both the OLT and an ONU. The OLT (or ONU) generates first and second random values, generates an authentication request frame containing the random values, and transmits it to the ONU (or OLT). The ONU generates a first hash value according to a hash function using the random values contained in the request frame, and transmits an authentication response frame containing the first hash value to the OLT. The OLT compares the first hash value with a second hash value calculated by it according to the has function using the two random values and an authentication key distributed to it, and transmits an authentication result frame to the ONU.

Abstract: A high-speed Galois Counter Mode-Advanced Encryption Standard (GCM-AES) block cipher apparatus and method is provided. The apparatus can operate at a low clock frequency of 125 MHz and provide a 2 Gbps link encryption function in an Optical Line Termination (OLT) and an Optical Network Unit (ONU) of an Ethernet Passive Optical Network (EPON). 11-round block cipher of 128-bit input data is implemented using an 8-round Counter-AES (CTR-AES) block cipher module and a 3-round CTR-AES block cipher module, so that it is possible to provide a 1 Gbps link security function for an input frequency of 62.5 MHz and a 2 Gbps link security function for an input frequency of 125 MHz.

Abstract: A non-volatile memory device according to some embodiments of the invention includes a number of memory cells and a word line voltage generator circuit. The word line voltage generator circuit generates a program voltage that is applied to the memory cells every program loop of a program cycle. The word line voltage generator circuit may generate a program voltage for one program loop that is different from a program voltage for each of the remaining program loops. Other embodiments are described and claimed.

Abstract: In a non-volatile semiconductor memory device which differentially uses a start programming voltage during a programming operation mode in order to reduce a dispersion for the number of programming loops, the programming method includes previously storing a row address that indicates at least one specific word line among a plurality of word lines; and applying a start programming voltage to the specific word line, when a row address applied in a programming operation mode coincides with the stored row address, the start programming voltage having a level that is different from a level of start programming voltage to be applied to the rest word lines except the specific word line, whereby reducing dispersion for the programming loop number and realizing a high-speed programming operation and operating efficiency.