Patents by Inventor Kyeong Han

Kyeong Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6882570
    Abstract: Embodiments of the invention provide a power-on reset function that establishes logic circuits in a memory chip at an initial stable state and a power-on read function that triggers a read operation of the memory chip. A first voltage detector output signal transitions when a power supply voltage reaches a first voltage, setting the logic circuits at the initial stable state. A second voltage detector output signal transitions when the power supply voltage reaches a second voltage, placing a latch in a set state that results in activation of a power-on read signal. A power-on read operation is carried out according to the activation of the power-on read signal. If the power supply voltage is not lowered below the first voltage, the second voltage detector output signal does not transition. Accordingly, embodiments are capable of preventing power-on read operations that are unnecessarily performed owing to power noise.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: April 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seok Byeon, Kyeong-Han Lee
  • Publication number: 20050036369
    Abstract: A nonvolatile semiconductor memory device compensates for temperature changes by holding constant a bit line precharge level. A memory device according to the present invention may include an electrically programmable memory cell array connected to a plurality of word lines and a plurality of bit lines, a bit line voltage supplying circuit for supplying a bit line voltage to the bit lines, a shut-off circuit connecting the memory cell array and the bit line voltage supplying circuit, and a shut-off controlling circuit for controlling the shut off circuit. The shut-off controlling circuit may be constructed to compensate for temperature changes in order to hold the bit-line precharge level constant.
    Type: Application
    Filed: July 1, 2004
    Publication date: February 17, 2005
    Inventors: Kyeong-Han Lee, Sung-Soo Lee
  • Patent number: 6853585
    Abstract: A flash memory device including a memory cell array block including a plurality of flash memory cells. A program verify voltage generating unit variably generates a program verify voltage that verifies flash memory cells programming. A wordline level selecting unit transfers the program verify voltage to the flash memory cells. And a page buffer, including a latch, stores flash memory cell data and resets the latch whenever the program verify voltage is lowered.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 8, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyeong-Han Lee, Sung-Soo Lee
  • Publication number: 20040109352
    Abstract: A flash memory device including a memory cell array block including a plurality of flash memory cells. A program verify voltage generating unit variably generates a program verify voltage that verifies flash memory cells programming. A wordline level selecting unit transfers the program verify voltage to the flash memory cells. And a page buffer, including a latch, stores flash memory cell data and resets the latch whenever the program verify voltage is lowered.
    Type: Application
    Filed: October 27, 2003
    Publication date: June 10, 2004
    Inventors: Kyeong-Han Lee, Sung-Soo Lee
  • Publication number: 20030223271
    Abstract: Embodiments of the invention provide a power-on reset function that establishes logic circuits in a memory chip at an initial stable state and a power-on read function that triggers a read operation of the memory chip. A first voltage detector output signal transitions when a power supply voltage reaches a first voltage, setting the logic circuits at the initial stable state. A second voltage detector output signal transitions when the power supply voltage reaches a second voltage, placing a latch in a set state that results in activation of a power-on read signal. A power-on read operation is carried out according to the activation of the power-on read signal. If the power supply voltage is not lowered below the first voltage, the second voltage detector output signal does not transition. Accordingly, embodiments are capable of preventing power-on read operations that are unnecessarily performed owing to power noise.
    Type: Application
    Filed: March 27, 2003
    Publication date: December 4, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seok Byeon, Kyeong-Han Lee