Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal.

Abstract: There are provided a substrate treating apparatus and a substrate treating method. The substrate treating apparatus includes: a stage on which a substrate is seated, in a chamber; and a treatment liquid supply apparatus supplying a treatment liquid containing a solvent and a solute onto the substrate, wherein the treatment liquid supply apparatus supplies the treatment liquid onto the substrate while moving from a center of the substrate to an outer peripheral surface of the substrate.

Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Abstract: An exemplary embodiment of the present invention provides a substrate treating method including removing particles formed on a substrate by continuously performing a process of supplying a treatment liquid including a polymer and a solvent onto the substrate, forming a solidified liquid film by volatilizing the solvent in the treatment liquid, removing the solidified liquid film from the substrate by supplying a stripping liquid onto the substrate; and supplying a rinse liquid onto the substrate.

Abstract: A battery module includes a cell stack including a plurality of a battery cell, a module case at least partially accommodating the cell stack, and a cooling unit disposed at one side of the cell stack. The battery cell includes a cell case, an electrode assembly and an electrolyte accommodated in the cell case, and an electrolyte storage unit inserted into the cell case to supply a supplementary electrolyte. The electrolyte storage unit is disposed between the electrode assembly and the cooling unit in a cross-sectional view.

Abstract: A cassette for receiving at least one substrate for a display device includes a base; and a first wall extending in a direction generally perpendicular to an upper surface of the base and a plurality of first projections extending from the first wall in a first direction and arranged in a second direction generally perpendicular to the first direction at substantially regular intervals. A first opening is defined between adjacent first projections to receive one end of a first substrate, the first opening includes a first portion having a first width in the second direction and a second portion having a second width greater than the first width, and the first portion is disposed closer to the first wall than the second portion.

Abstract: Provided are a substrate treatment apparatus and method for treating a substrate by simultaneously providing a stripper for peeling a coating film on the substrate to an entire surface of the substrate. The substrate treatment method includes discharging a first liquid onto a substrate by using a first nozzle, and forming a coating film collecting particles by using the first liquid; spraying a second liquid on the substrate by using a second nozzle, and peeling the coating film from the substrate by using the second liquid; and discharging a third liquid onto the substrate by using a third nozzle, and rinsing the coating film from the substrate by using the third liquid, wherein in the peeling of the coating film, the second liquid is simultaneously sprayed on an entire surface of the substrate.

Abstract: Disclosed is a method for controlling an energy management system that is performed by a computing device including at least one processor. The method may include acquiring a target temperature of one or more target points; and controlling one or more control variables using a reinforcement learning control model trained for a first condition regarding a state before a current temperature of the target points converges to the target temperature.

Abstract: A semiconductor package may include: a substrate having a first side and a second side on a same plane; a first semiconductor chip disposed over the second side of the substrate; a first one-side third semiconductor chip stack disposed over the first side of the substrate and spaced apart from the first semiconductor chip; a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack, wherein each of the third semiconductor chip stacks includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the third semiconductor chips are farther from the substrate, each of the third semiconductor chip stacks being electrically connected to the substrate.

Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

Abstract: A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n?1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

Abstract: A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

Abstract: A cassette for receiving at least one substrate for a display device includes a base; and a first wall extending in a direction generally perpendicular to an upper surface of the base and a plurality of first projections extending from the first wall in a first direction and arranged in a second direction generally perpendicular to the first direction at substantially regular intervals. A first opening is defined between adjacent first projections to receive one end of a first substrate, the first opening includes a first portion having a first width in the second direction and a second portion having a second width greater than the first width, and the first portion is disposed closer to the first wall than the second portion.

Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.

Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

Abstract: A tray includes a main body portion including a bottom surface portion and a sidewall portion; and a plurality of first guide portions disposed on the bottom surface portion and arranged to be spaced apart from each other in a first direction. Each of the first guide portions includes a first main protruding portion, a first sub-protruding portion which protrudes from the first main protruding portion in the first direction, and a second sub-protruding portion which protrudes from the first main protruding portion in a direction opposite to the first direction, and the first sub-protruding portion and the second sub-protruding portion are alternately arranged in a direction the first main protruding portion extends.

Abstract: A cassette for receiving at least one substrate for a display device includes a base; and a first wall extending in a direction generally perpendicular to an upper surface of the base and a plurality of first projections extending from the first wall in a first direction and arranged in a second direction generally perpendicular to the first direction at substantially regular intervals. A first opening is defined between adjacent first projections to receive one end of a first substrate, the first opening includes a first portion having a first width in the second direction and a second portion having a second width greater than the first width, and the first portion is disposed closer to the first wall than the second portion.

Abstract: Disclosed is a method for controlling an energy management system that is performed by a computing device including at least one processor. The method may include acquiring a target temperature of one or more target points; and controlling one or more control variables using a reinforcement learning control model trained for a first condition regarding a state before a current temperature of the target points converges to the target temperature.