Abstract: A device includes a computing bit cell, and a control circuit that controls the computing bit cell. The computing bit cell includes a memory cell that stores a coefficient bit and first to third transistors. The first transistor is connected between a first node and a ground node and has a gate that is connected to a first line which extends in a first direction and which receives a voltage based on a first input bit. The second transistor is connected between a second node and a second line that extends in a second direction that crosses the first direction, the second transistor having a gate that receives a pre-charge enable signal, the second line receiving a voltage based on a second input bit. The third transistor is connected between the first node and the second node and has a gate connected to the memory cell.

Abstract: The present disclosure provides a driving unit of a steering apparatus configured to provide an auxiliary torque of a steering apparatus and including a driving housing having an installation region formed therein, and the driving unit includes a worm shaft disposed in the installation region and having a worm gear formed therein, a first bearing rotatably supporting one side of the worm shaft, a damper penetrating and supporting one side of the worm shaft supported by the first bearing, and a stopper penetrating and supporting one side of the worm shaft passing through the damper, one end of the stopper being spaced apart from the damper so that a movement of the damper is limited in an axial direction of the worm shaft.

Abstract: An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

Abstract: A bearing is disposed between a steering shaft and an inner column covering at least a part of the steering shaft. The bearing includes: an inner ring supporting an outer circumference of the steering shaft and having an elastically deformable material such as a plastic-containing material; an outer ring of which at least a part faces an inner circumference of the inner column; and a roller rotatably disposed between the inner ring and the outer ring. The bearing may be included in a steering apparatus.

Abstract: Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.

Abstract: The present disclosure is direction to a stopper disposed in a driver for a steering apparatus which includes a worm gear, a bearing supporting rotation of the worm gear, and a damper buffering an impact of the bearing is provided, the stopper including: an annular body having a through hole therein allowing one side of the worm gear to pass through; and a leg on the annular body to protrude toward the damper along an axial direction of the worm gear.

Abstract: A bearing and a steering apparatus including the same are provided. A bearing is disposed between a steering shaft and an inner column covering at least a part of the steering shaft. The bearing includes: an inner ring supporting an outer circumference of the steering shaft and having an elastically deformable material such as a plastic-containing material; an outer ring of which at least a part faces an inner circumference of the inner column; and a roller rotatably disposed between the inner ring and the outer ring.

Abstract: Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.

Abstract: An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

Abstract: A speed reducer for an electric power steering system according to an embodiment of the present disclosure includes a gear housing, a plurality of air flow passages, and check valves. The gear housing accommodates a worm shaft and a worm wheel. The plurality of air flow passages is formed in the gear housing and connects the outside of the gear housing and a sealed space formed in the gear housing. The check valves are respectively disposed in the plurality of air flow passages.

Abstract: An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

Abstract: A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

Abstract: The present disclosure provides a driving unit of a steering apparatus configured to provide an auxiliary torque of a steering apparatus and including a driving housing having an installation region formed therein, and the driving unit includes a worm shaft disposed in the installation region and having a worm gear formed therein, a first bearing rotatably supporting one side of the worm shaft, a damper penetrating and supporting one side of the worm shaft supported by the first bearing, and a stopper penetrating and supporting one side of the worm shaft passing through the damper, one end of the stopper being spaced apart from the damper so that a movement of the damper is limited in an axial direction of the worm shaft.

Abstract: The present disclosure is direction to a stopper disposed in a driver for a steering apparatus which includes a worm gear, a bearing supporting rotation of the worm gear, and a damper buffering an impact of the bearing is provided, the stopper including: an annular body having a through hole therein allowing one side of the worm gear to pass through; and a leg on the annular body to protrude toward the damper along an axial direction of the worm gear.

Abstract: An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.

Abstract: A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

Abstract: Embodiments according to the application relates to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths for an oversampling ADC, which can increase or improve an overall performance of the circuit.

Abstract: The present invention relates to an apparatus and a method for measuring an in phase and quadrature (IQ) imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.

Abstract: The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.

Abstract: The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.