Patents by Inventor Kyeongho Lee

Kyeongho Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8243579
    Abstract: Embodiments according to the application relates to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths for an oversampling ADC, which can increase or improve an overall performance of the circuit.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 14, 2012
    Assignee: GCT Semiconductor, Inc.
    Inventors: Seung-Wook Lee, Joonbae Park, Jeong Woo Lee, Su Won Kang, Kyeongho Lee
  • Patent number: 8229028
    Abstract: The present invention relates to an apparatus and a method for measuring an in phase and quadrature (IQ) imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 24, 2012
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kyeongho Lee, Joonbae Park, Jeong Woo Lee, Seung-Wook Lee, Eal Wan Lee
  • Patent number: 8018990
    Abstract: The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: September 13, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kyeongho Lee, Joonbae Park, Jeong Woo Lee, Seung-Wook Lee, Eal Wan Lee
  • Patent number: 7995645
    Abstract: The present general inventive concept relates to apparatuses and/or methods for measuring an in-phase and quadrature (IQ) imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: August 9, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kyeongho Lee, Joonbae Park, Jeong Woo Lee, Seung-Wook Lee, Eal Wan Lee
  • Patent number: 7952442
    Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: May 31, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
  • Patent number: 7952435
    Abstract: Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: May 31, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Seung-Wook Lee, Joonbac Park, Jeong Woo Lee, Su Won Kang, Kyeongho Lee
  • Patent number: 7949324
    Abstract: The application discloses embodiments of methods and/or systems for compensating a transmission carrier leakage of an up-conversion mixer, a tranceiving circuit or apparatus embodying the same. One embodiment of a method can include detecting an I channel DC offset DCI0 and a Q channel DC offset DCQ0 generated by a reception carrier leakage from an output of a down-conversion mixer, detecting an I channel DC offset DCI and a Q channel DC offset DCQ from the output of the down-conversion mixer while varying a compensation parameter being inputted to an up-conversion mixer that has its output coupled to an input of the down-conversion mixer to determine the compensation parameter that can reduce or minimize a transmission carrier leakage. A combination of a transmission baseband signal and the determined compensation parameter can be transmitted using the up-conversion mixer and an antenna to compensate for the transmission carrier leakage.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 24, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Kyeongho Lee, Sang Hun Jung, Eal Wan Lee, In Ho Song
  • Patent number: 7945208
    Abstract: Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: May 17, 2011
    Assignee: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Kyeongho Lee, Yido Koo, Jeong Woo Lee
  • Patent number: 7925217
    Abstract: Embodiments of methods receiving circuits and apparatuses compensate for an IQ mismatch using a test signal positioned in a guard band. One embodiment of a method can include converting a sum of a received signal and a test signal positioned in a guard band to a first signal and a second signal of an intermediate frequency or a base band using an IQ mixer, detecting the IQ mismatch using the test signal respectively included in subsequent signals corresponding to the first signal and the second signal and compensating for the detected IQ mismatch using the IQ mismatch.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 12, 2011
    Assignee: GCT Research, Inc.
    Inventors: Joonbae Park, Kyeongho Lee
  • Patent number: 7831215
    Abstract: Embodiments of methods, transceiver circuits, and systems can compensate an IQ mismatch (e.g., Tx or Rx) or a carrier leakage using a plurality of local oscillators. One embodiment of a transceiver can include a first up-conversion IQ mixer, a second up-conversion IQ mixer, a first down-conversion IQ mixer with an input to receive an output of the second up-conversion IQ mixer, a second down-conversion IQ mixer with an input to receive an output of the first up-conversion IQ mixer, a first local oscillator to generate a first IQ LO signal for the first up-conversion IQ mixer and the first down-conversion IQ mixer, and a second local oscillator to generate a second IQ LO signal for the second up-conversion IQ mixer and the second down-conversion IQ mixer.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: November 9, 2010
    Assignee: GCT Research, Inc.
    Inventors: Joonbae Park, Kyeongho Lee
  • Patent number: 7812672
    Abstract: Embodiments of the present general inventive concept include a low noise amplifier and method with an improved linearity while reducing a noise disadvantage (e.g., increase). One embodiment of a low noise amplifier can include a first transistor to receive an input signal at a control terminal thereof, a second transistor having a first terminal coupled to a second terminal of the first transistor, an envelope detector to output a control signal corresponding to a characteristic of the input signal and an envelope amplifier to amplify the control signal to be applied to a control terminal of the second transistor.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 12, 2010
    Assignee: GCT Semiconductor, Inc.
    Inventors: Seung-Wook Lee, Deok Hee Lee, Eunseok Song, Joonbae Park, Kyeongho Lee
  • Patent number: 7768097
    Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: August 3, 2010
    Assignee: GCT Semiconductor, Inc.
    Inventors: Yido Koo, Hyungki Huh, Kang Yoon Lee, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
  • Patent number: 7606293
    Abstract: A bidirectional turbo ISI canceller cancels precursor-ISI as well as postcursor-ISI in a received signal without incorporating a multiplicative feedforward equalization filter. This is accomplished by taking a three-step receiver design approach. In the first step, an optimal single-symbol RAKE receiver is designed to comprise a CMF, a codeword correlator bank, and an energy bias (EB) canceller under the assumption that no ISI is generated by preceding or trailing symbols. In a second step, a DFE is included for suppressing postcursor-ISI caused by a preceding symbol. Finally, a precursor ISI canceler is used to remove the remaining ISI caused by a trailing symbol. All three components may be integrated into a BTIC-based receiver applying turbo-iteration processing.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: October 20, 2009
    Assignee: GCT Semiconductor, Inc.
    Inventors: Byoung-Hoon Kim, Suwon Kang, Bong Youl Cho, Kyeongho Lee
  • Patent number: 7560960
    Abstract: The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: July 14, 2009
    Assignee: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Kyeongho Lee, Yido Koo, Jeong-Woo Lee
  • Patent number: 7535977
    Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: May 19, 2009
    Assignee: GCT Semiconductor, Inc.
    Inventors: Yido Koo, Youngho Ahn, Eunseok Song, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
  • Patent number: 7515662
    Abstract: Embodiments of methods and apparatuses can compensate gain ripple and/or group delay characteristics of at least one filter, a receiving circuit embodying a filter, or a communication system having a wireless terminal embodying the receiving circuit.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: April 7, 2009
    Assignee: GCT Semiconductor, Inc.
    Inventors: Joonbae Park, Kyeongho Lee
  • Patent number: 7512390
    Abstract: An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: March 31, 2009
    Assignee: GCT Semiconductor, Inc.
    Inventors: Kang Yoon Lee, Yido Koo, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee
  • Publication number: 20090028231
    Abstract: The present invention relates to an apparatus and a method for measuring an IQ imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance.
    Type: Application
    Filed: February 20, 2008
    Publication date: January 29, 2009
    Inventors: Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Eal Wan Lee
  • Publication number: 20080252383
    Abstract: Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.
    Type: Application
    Filed: October 29, 2007
    Publication date: October 16, 2008
    Inventors: Seung Wook Lee, Joonbac Park, Jeong Woo Lee, Su Won Kang, Kyeongho Lee
  • Publication number: 20080253277
    Abstract: Embodiments according to the application relates to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths for an oversampling ADC, which can increase or improve an overall performance of the circuit.
    Type: Application
    Filed: October 29, 2007
    Publication date: October 16, 2008
    Inventors: Seung Wook Lee, Joonbae Park, Jeong Woo Lee, Su Won Kang, Kyeongho Lee