Abstract: Embodiments of methods and systems of the application can transmit data (e.g., voice) using a wireless LAN and a Bluetooth. One system embodiment can include a terminal device, an AP (access point) for communicating with the terminal device according to a first (e.g., wireless LAN) protocol by using a first frequency band among multiple frequency bands of a prescribed frequency band (e.g., ISM frequency band) and a headset for communicating with the terminal device according to a second (e.g., Bluetooth) protocol by using at least one frequency band of remaining frequency bands by excepting the first frequency band.

Abstract: Embodiments of a clock generator and a clock generating method can use a delay locked loop (DLL). In one embodiment, a clock generator can include a first oscillator to generate a first clock signal having a frequency corresponding to a control signal, a delay locked loop to generate a second clock signal having a frequency higher than that of the first clock signal, a frequency divider to receive the second clock signal to generate a third clock signal having a frequency lower than that of the second clock signal, a second oscillator to generate a fourth clock signal and a phase frequency detector to generate the control signal corresponding to a phase difference and/or a frequency difference between the third clock signal and the fourth clock signal.

Abstract: Embodiments include a serial interface circuit, serial interface method and an apparatus including a serial interface circuit. Embodiments of a serial interface circuit can include a frequency divider implemented by using a counter instead of a PLL. One embodiment of a serial interface circuit can include a data receiver to receive first serial data, a serial-parallel converter to convert the first serial data from the data receiver to first parallel data, a clock receiver to receive a first clock signal having a frequency corresponding to the first serial data, and a frequency divider coupled to the clock receiver to generate a second clock signal having a frequency corresponding to the first parallel data with the first clock signal where the frequency divider is configured with a counter.

Abstract: Embodiments of methods and apparatuses can compensate gain ripple and/or group delay characteristics of at least one filter, a receiving circuit embodying a filter, or a communication system having a wireless terminal embodying the receiving circuit.

Abstract: Embodiments of methods, transceiver circuits, and systems can compensate an IQ mismatch (e.g., Tx or Rx) or a carrier leakage using a plurality of local oscillators. One embodiment of a transceiver can include a first up-conversion IQ mixer, a second up-conversion IQ mixer, a first down-conversion IQ mixer with an input to receive an output of the second up-conversion IQ mixer, a second down-conversion IQ mixer with an input to receive an output of the first up-conversion IQ mixer, a first local oscillator to generate a first IQ LO signal for the first up-conversion IQ mixer and the first down-conversion IQ mixer, and a second local oscillator to generate a second IQ LO signal for the second up-conversion IQ mixer and the second down-conversion IQ mixer.

Abstract: Embodiments of methods receiving circuits and apparatuses compensate for an IQ mismatch using a test signal positioned in a guard band. One embodiment of a method can include converting a sum of a received signal and a test signal positioned in a guard band to a first signal and a second signal of an intermediate frequency or a base band using an IQ mixer, detecting the IQ mismatch using the test signal respectively included in subsequent signals corresponding to the first signal and the second signal and compensating for the detected IQ mismatch using the IQ mismatch.

Abstract: A variable-gain amplifier circuit uses a pair of single-ended operational amplifiers to amplify complementary portions of a differential input signal. By using two single-ended amplifiers instead of a single differential amplifier, linearity is significantly improved. In addition, common mode feedback circuitry is eliminated along with harmonic distortion and other forms of noise which tend to negative affect the quality of the signal output from the circuit.

Abstract: An apparatus and method of oscillating a wideband frequency are disclosed. The apparatus includes: a frequency oscillating unit for oscillating a predetermined frequency; a phase-locked loop for comparing the oscillated frequency and a reference frequency by feed-backing the oscillated frequency from the frequency oscillating unit and fixing an oscillating frequency of the frequency oscillating unit; and a variable dividing unit for varying a division ratio to approach to a frequency band required by the oscillating frequency and dividing the oscillating frequency.

Abstract: A wireless receiver and a wireless receiving method are provided wherein a frequency of a radio frequency (RF) is down-converted into a frequency of a substantially zero intermediate frequency (IF) signal or a substantially low IF signal. The down-converted signal may be filtered by an integrated filter having a low quality factor and then up-converted again into a particular IF signal, thereby integrating an external element. For example, a receiving device may receive a RF signal in a required band. A frequency down-converting device may down-convert a frequency so that a center frequency of the RF signal becomes zero. A channel select filtering device may select a required channel from the signals whose frequency is down-converted. An IF signal converting device may up-convert a frequency of the channel selected signal into a required IF. An IF processing device may extract a baseband signal after the converted IF signal is inputted and processed.

Abstract: An apparatus and method of oscillating a wideband frequency are disclosed. The apparatus includes: a frequency oscillating unit for oscillating a predetermined frequency; a phase-locked loop for comparing the oscillated frequency and a reference frequency by feed-backing the oscillated frequency from the frequency oscillating unit and fixing an oscillating frequency of the frequency oscillating unit; and a variable dividing unit for varying a division ratio to approach to a frequency band required by the oscillating frequency and dividing the oscillating frequency.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors.

Abstract: A DC offset cancelling circuit with multiple feedback loops suppresses DC offset voltages within an automatic gain control loop apparatus. The apparatus includes a plurality of gain stages connected in series that receive and amplify an input RF signal. Each gain stage includes a corresponding feedback loop to filter the DC offset voltage accumulated in the respective gain stage.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

Abstract: A system and method for filtering signals in a communications system reduces hardware and chip size requirements by selectively connecting a filter along transmitter and receiver paths of a transceiver. In operation, a controller generated signals for connecting the filter along the transmitter path when the transceiver is in transmitter mode and for connecting the filter along the receiver path when the transmitter is in receiver mode. The controller then generates additional signals for setting one or more parameters of the filter based on the path connected, or put differently based on the operational mode of the transceiver. In a variation, the controller sets the parameters of additional elements coupled to the filter as a way of further controlling processing of the transmitter and receiver signals.

Abstract: The present invention is directed to a linearization apparatus and method. Preferred embodiments according to the present invention can combine an auxiliary non-linear block to a functional block of a system to increase linearity of an output signal of the system such as a communication system. System overhead due to the non-linear auxiliary block can be small because of circuit structure, cost and low consumption. Further, the non-linear auxiliary block can be designed so that no feedback path is required. Further preferred embodiments can use a feedback path without loss of stability by using a cancellation apparatus or process based on an averaging detection of the output signal. For example, a feedback loop can detect power leakage in a sideband caused by non-linearities of the communication system.

Abstract: A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Abstract: A variable-gain amplifier circuit uses a pair of single-ended operational amplifiers to amplify complementary portions of a differential input signal. By using two single-ended amplifiers instead of a single differential amplifier, linearity is significantly improved. In addition, common mode feedback circuitry is eliminated along with harmonic distortion and other forms of noise which tend to negative affect the quality of the signal output from the circuit.

Abstract: An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal.

Abstract: A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency.