Patents by Inventor Kyle Jordan

Kyle Jordan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250038003
    Abstract: Molybdenum-containing films are deposited on semiconductor substrates at relatively low temperatures of between about 100 and about 500° C., such as between about 200 and about 450° C. For example, molybdenum metal can be deposited at this temperature on a substrate having exposed metal and exposed dielectric in a substantially non-selective manner. In one implementation, a substrate having a recessed feature is provided, where the recessed feature has an exposed dielectric on the sidewalls and an exposed metal on the bottom. The substrate is exposed to a molybdenum-containing precursor, a reducing agent, and a silicon-containing reagent, to thereby reduce the molybdenum-containing precursor and form a molybdenum-containing layer that includes metallic molybdenum. The use of the silicon-containing reactant leads to a reduction in on-metal/on-dielectric selectivity of molybdenum deposition.
    Type: Application
    Filed: December 2, 2022
    Publication date: January 30, 2025
    Applicant: Lam Research Corporation
    Inventors: David Joseph Mandia, Kyle Jordan Blakeney, Chiukin Steven Lai
  • Publication number: 20250014967
    Abstract: Systems, apparatus, articles of manufacture, and methods to improve thermal dissipation and mechanical loading of integrated circuit packages are disclosed. An example apparatus includes: a socket to receive an integrated circuit package; and a plate to apply a load on the integrated circuit package towards the socket. The plate includes an internal channel to carry a coolant through the plate. The liquid coolant is to facilitate cooling of the integrated circuit package.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Applicant: Intel Corporation
    Inventors: Kyle Jordan Arrington, Prabhakar Subrahmanyam, Steven Adam Klein, Kelly Porter Lofgreen, Joseph Blane Petrini
  • Publication number: 20240232154
    Abstract: A system for analyzing distinct datasets with a common index is configurable to (i) receive input data that includes a first set of data and a second set of data that share a common index; (ii) perform a clustering operation on the first set of data to generate a set of clustered data comprising groups representing related datapoints; (iii) identify a set of occurrences within the second set of data (where each occurrence is associated with a respective set of coordinates in the common index), (iv) for each of the set of occurrences: (a) localize search space(s) in the common index using the respective set of coordinates for the occurrence, and (b) facilitate analysis of group(s) of the set of clustered data that are located within the search space(s) to determine whether a relationship exists between the group(s) and the occurrence.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 11, 2024
    Inventors: Andrew Craig Hardwick, Kyle Jordan Russell
  • Publication number: 20240219654
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20240222257
    Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Ziyin Lin, Rahul N. Manepalli, Brandon C. Marin, Jeremy D. Ecton
  • Publication number: 20240222210
    Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240222243
    Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240219659
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20240219660
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Yiqun Bai, Dingying Xu, Eric J.M. Moret, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Bin Mu
  • Publication number: 20240219656
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20240219655
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Bai Nie, Brandon C. Marin, Dingying Xu, Gang Duan, Hongxia Feng, Jeremy D. Ecton, Kristof Darmawikarta, Kyle Jordan Arrington, Srinivas Venkata Ramanuja Pietambaram, Xiaoying Guo, Yiqun Bai, Ziyin Lin
  • Publication number: 20240222136
    Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ashay A. Dani, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Wei Wei, Ziyin Lin
  • Publication number: 20240222238
    Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Bai Nie, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
  • Publication number: 20240215269
    Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington
  • Publication number: 20240213169
    Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
  • Publication number: 20240213170
    Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
  • Publication number: 20240143918
    Abstract: A system for facilitating text analysis is configurable to (i) receive input text data comprising a set of reference text and at least a first set of text, wherein the set of reference text and the first set of text each comprise structured components; process the input text data utilizing a syntax and verb usage module of a natural language processing (NLP) layer; generate a mapping of structured components of the first set of text to structured components of the set of reference text by processing output of the syntax and verb usage module utilizing a similarity analysis module or a categorization module of the NLP layer; and generate an output depicting one or more aspects of the mapping.
    Type: Application
    Filed: August 18, 2023
    Publication date: May 2, 2024
    Inventors: JoAnna Jean Butler, Casey Hatcher Cooper, Jaden Kadesh Flint, Jason LeVoy Rogers, Keith Boyd Zook, Kyle Jordan Russell
  • Publication number: 20240052486
    Abstract: Molybdenum-containing films are deposited on semiconductor substrates using reactions of molybdenum-containing precursors in ALD and CVD processes. In some embodiments, the precursors can be used for deposition of molybdenum metal films with low levels of incorporation of carbon and nitrogen. In some embodiments, the films are deposited using fluorine-free precursors in a presence of exposed silicon-containing layers without using etch stop layers. The precursor, in some embodiments, is a compound that includes molybdenum, at least one halogen that forms a bond with molybdenum, and at least one organic ligand that includes an element selected from the group consisting of N, O, and S, that forms a bond with molybdenum. In another aspect, the precursor is a molybdenum compound with at least one sulfur-containing ligand, and preferably no molybdenum-carbon bonds.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 15, 2024
    Inventor: Kyle Jordan BLAKENEY
  • Patent number: 11881008
    Abstract: The disclosed techniques are focused on processes for encoding an enhanced image with non-image data. Notably, the “non-image data” is distinct from “image data” in that the image data defines display characteristics of an image (e.g., display properties of a pixel) while the non-image data is unrestricted and can describe any data, even data different than display characteristics. An image is accessed, where the image includes at least one pixel that is associated with at least one color channel. Non-image data is encoded into the color channel. An index, which maps where the non-image data has been encoded in the color channel of the pixel, is generated or modified. As a result of encoding the non-image data into the color channel, an enhanced image is generated.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 23, 2024
    Assignee: INTUITIVE RESEARCH AND TECHNOLOGY CORPORATION
    Inventors: Kyle Jordan Russell, Chanler Megan Crowe Cantor
  • Patent number: 11821071
    Abstract: Molybdenum-containing films are deposited on semiconductor substrates using reactions of molybdenum-containing precursors in ALD and CVD processes. In some embodiments, the precursors can be used for deposition of molybdenum metal films with low levels of incorporation of carbon and nitrogen. In some embodiments, the films are deposited using fluorine-free precursors in a presence of exposed silicon-containing layers without using etch stop layers. The precursor, in some embodiments, is a compound that includes molybdenum, at least one halogen that forms a bond with molybdenum, and at chamber least one organic ligand that includes an element selected from the group consisting of N, O, and S, that forms a bond with molybdenum, In another aspect, the precursor is a molybdenum, compound with at least one sulfur-containing ligand, and preferably no molybdenum-carbon bonds.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 21, 2023
    Assignee: Lam Research Corporation
    Inventor: Kyle Jordan Blakeney