Patents by Inventor Kyle Jordan
Kyle Jordan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240222210Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
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Publication number: 20240219654Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20240219656Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Ziyin Lin, Yiqun Bai, Bohan Shan, Kyle Jordan Arrington, Haobo Chen, Dingying Xu, Robert Alan May, Gang Duan, Bai Nie, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20240219660Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Hongxia Feng, Haobo Chen, Yiqun Bai, Dingying Xu, Eric J.M. Moret, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Bin Mu
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Publication number: 20240222243Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
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Publication number: 20240222257Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Ziyin Lin, Rahul N. Manepalli, Brandon C. Marin, Jeremy D. Ecton
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Publication number: 20240213170Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Applicant: Intel CorporationInventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
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Publication number: 20240215269Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington
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Publication number: 20240213169Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.Type: ApplicationFiled: December 21, 2022Publication date: June 27, 2024Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
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Publication number: 20240143918Abstract: A system for facilitating text analysis is configurable to (i) receive input text data comprising a set of reference text and at least a first set of text, wherein the set of reference text and the first set of text each comprise structured components; process the input text data utilizing a syntax and verb usage module of a natural language processing (NLP) layer; generate a mapping of structured components of the first set of text to structured components of the set of reference text by processing output of the syntax and verb usage module utilizing a similarity analysis module or a categorization module of the NLP layer; and generate an output depicting one or more aspects of the mapping.Type: ApplicationFiled: August 18, 2023Publication date: May 2, 2024Inventors: JoAnna Jean Butler, Casey Hatcher Cooper, Jaden Kadesh Flint, Jason LeVoy Rogers, Keith Boyd Zook, Kyle Jordan Russell
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Publication number: 20240052486Abstract: Molybdenum-containing films are deposited on semiconductor substrates using reactions of molybdenum-containing precursors in ALD and CVD processes. In some embodiments, the precursors can be used for deposition of molybdenum metal films with low levels of incorporation of carbon and nitrogen. In some embodiments, the films are deposited using fluorine-free precursors in a presence of exposed silicon-containing layers without using etch stop layers. The precursor, in some embodiments, is a compound that includes molybdenum, at least one halogen that forms a bond with molybdenum, and at least one organic ligand that includes an element selected from the group consisting of N, O, and S, that forms a bond with molybdenum. In another aspect, the precursor is a molybdenum compound with at least one sulfur-containing ligand, and preferably no molybdenum-carbon bonds.Type: ApplicationFiled: October 12, 2023Publication date: February 15, 2024Inventor: Kyle Jordan BLAKENEY
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Patent number: 11881008Abstract: The disclosed techniques are focused on processes for encoding an enhanced image with non-image data. Notably, the “non-image data” is distinct from “image data” in that the image data defines display characteristics of an image (e.g., display properties of a pixel) while the non-image data is unrestricted and can describe any data, even data different than display characteristics. An image is accessed, where the image includes at least one pixel that is associated with at least one color channel. Non-image data is encoded into the color channel. An index, which maps where the non-image data has been encoded in the color channel of the pixel, is generated or modified. As a result of encoding the non-image data into the color channel, an enhanced image is generated.Type: GrantFiled: May 12, 2021Date of Patent: January 23, 2024Assignee: INTUITIVE RESEARCH AND TECHNOLOGY CORPORATIONInventors: Kyle Jordan Russell, Chanler Megan Crowe Cantor
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Patent number: 11821071Abstract: Molybdenum-containing films are deposited on semiconductor substrates using reactions of molybdenum-containing precursors in ALD and CVD processes. In some embodiments, the precursors can be used for deposition of molybdenum metal films with low levels of incorporation of carbon and nitrogen. In some embodiments, the films are deposited using fluorine-free precursors in a presence of exposed silicon-containing layers without using etch stop layers. The precursor, in some embodiments, is a compound that includes molybdenum, at least one halogen that forms a bond with molybdenum, and at chamber least one organic ligand that includes an element selected from the group consisting of N, O, and S, that forms a bond with molybdenum, In another aspect, the precursor is a molybdenum, compound with at least one sulfur-containing ligand, and preferably no molybdenum-carbon bonds.Type: GrantFiled: March 6, 2020Date of Patent: November 21, 2023Assignee: Lam Research CorporationInventor: Kyle Jordan Blakeney
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Publication number: 20230314946Abstract: The present disclosure relates to a film formed with a metal precursor and an organic precursor, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In particular embodiments, the film includes alternating layers of metal-containing layers and organic layers. In other embodiments, the film includes a matrix of deposited metal and organic constituents.Type: ApplicationFiled: July 16, 2021Publication date: October 5, 2023Inventors: Eric Calvin Hansen, Timothy William Weidman, Chenghao Wu, Qinghuang Lin, Kyle Jordan Blakeney, Adrien LaVoie, Sivananda Krishnan Kanakasabapathy, Samantha S.H. Tan, Richard Wise, Yang Pan, Younghee Lee, Katie Lynn Nardi, Kevin Li Gu, Boris Volosskiy
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Publication number: 20230298936Abstract: An electrically conductive structure in an integrated circuit (IC) includes recessed features in a dielectric layer filled with metal. The recessed features include a conformal, self-forming diffusion barrier and seed layer to limit oxidation of the metal into ions that will diffuse through the dielectric.Type: ApplicationFiled: August 10, 2021Publication date: September 21, 2023Inventors: Kyle Jordan Blakeney, Yezdi Dordi
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Publication number: 20230259025Abstract: The present disclosure relates to a film formed with a precursor and an organic co-reactant, as well as methods for forming and employing such films. The film can be employed as a photopatternable film or a radiation-sensitive film. In particular embodiments, the carbon content within the film can be tuned by decoupling the sources of the radiation-sensitive metal elements and the radiation-sensitive organic moieties during deposition. In non-limiting embodiments, the radiation can include extreme ultraviolet (EUV) or deep ultraviolet (DUV) radiation.Type: ApplicationFiled: July 16, 2021Publication date: August 17, 2023Inventors: Eric Calvin Hansen, Timothy William Weidman, Chenghao Wu, Qinghuang Lin, Kyle Jordan Blakeney
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Publication number: 20230260834Abstract: Various embodiments herein relate to methods, apparatus, and systems for forming an interconnect structure, or a portion thereof, on a substrate. In one example, the method includes receiving the substrate in a processing chamber, the substrate having dielectric material exposed within recessed features formed therein; exposing the substrate to plasma to thereby modify a top surface of the dielectric material; forming a metal oxide barrier layer on the modified top surface of the dielectric material, wherein the metal oxide barrier layer is formed through atomic layer deposition and/or chemical vapor deposition. In certain implementations, one or more additional step may be taken to improve processing results, for example to promote nucleation and/or adhesion of relevant layers.Type: ApplicationFiled: June 25, 2021Publication date: August 17, 2023Inventors: Lee J. BROGAN, Patrick A. VAN CLEEMPUT, Matthew Martin HUIE, Kyle Jordan BLAKENEY, Yi Hua LIU
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Publication number: 20230237612Abstract: A system for determining volume of a selectable region is configurable to (i) obtain user input directed to a 3D representation of a set of 2D images and (ii) based on the user input, selectively modify one or more mask pixels of one or more respective selection masks. Each 2D image of the set of 2D images is associated with a respective selection mask. The 3D representation represents pixels of the set of 2D images with corresponding voxels. The user input selects one or more voxels of the 3D representation. The one or more mask pixels is associated with one or more pixels of the set of 2D images that correspond to the one or more voxels of the 3D representation selected via the user input.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Inventors: James S. ROZNICK, Kyle Jordan RUSSELL
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Publication number: 20230229924Abstract: Techniques for updating a visualization of a neural network and for refining a neural network are disclosed. Network data is obtained, where this data describes the neural network. At least some of the network data is normalized. A visual representation of the neural network is generated. The visual representation includes a set of nodes. The visual representation further includes edges connecting various nodes. The visual representation is updated using the normalized network data. As a result of updating the visual representation using the normalized network data, a display of the nodes and/or of the edges is modified in a manner to reflect a relative relationship that exists between the nodes and/or the edges. The relative relationship is based on the normalized network data. The updated visual representation is then displayed.Type: ApplicationFiled: January 12, 2023Publication date: July 20, 2023Inventor: Kyle Jordan RUSSELL
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Patent number: 11679407Abstract: To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM?0.01-0.025° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.Type: GrantFiled: June 26, 2020Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Kyle Jordan Arrington, Joseph Blaine Petrini, Aaron McCann, Shankar Devasenathipathy, James Christopher Matayabas, Jr., Mostafa Aghazadeh, Jerrod Peterson