Patents by Inventor Kyle W. Patterson

Kyle W. Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8039389
    Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: October 18, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas M. Reber, Mark D. Hall, Kurt H. Junker, Kyle W. Patterson, Tab Allen Stephens, Edward K. Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Irene Wright
  • Patent number: 7199429
    Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: April 3, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas M. Reber, Mark D. Hall, Kurt H. Junker, Kyle W. Patterson, Tab Allen Stephens, Edward K. Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Irene Wright
  • Patent number: 6972255
    Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: December 6, 2005
    Assignees: Freescale Semiconductor, Inc., Advanced Micro Devices, Inc.
    Inventors: Douglas M. Reber, Mark D. Hall, Kurt H. Junker, Kyle W. Patterson, Tab Allen Stephens, Edward K. Theiss, Srikanteswara Dakshiina-Murthy, Marilyn Irene Wright