Patents by Inventor Kyohei Fukuda

Kyohei Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240083259
    Abstract: An electric vehicle including a motor as a driving source includes: an accelerator; a pseudo shifter mimicking a gear changing operation; a pseudo clutch mimicking a clutch operation; a detector detecting an operation mode performed on each of the accelerator, pseudo shifter, and pseudo clutch by a driver, and a rotation speed of a driving wheel; a reaction force generator generating a reaction force in the pseudo shifter in response to a driver operation performed thereon; and a controller determining the reaction force. The controller includes a processor and a memory coupled thereto. The processor calculates a virtual differential rotation speed that is based on a virtual engine rotation speed, mimicking an engine rotation speed when the driving source is assumed as being an engine, and the rotation speed based on a detection result of the detector, and determines the reaction force based on the virtual differential rotation speed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 14, 2024
    Applicant: SUBARU CORPORATION
    Inventors: Naonori IKEZAWA, Takahiro YAMAMOTO, Kiyofumi SATO, Hironao SATO, Kyohei YAMAMOTO, Hideto FUKUDA
  • Publication number: 20230356238
    Abstract: A particle collection vessel (2) which charges particles in air and then collects them includes a vessel body (7) having an opening (8); a suction part (14) provided in the opening (8) and having an inflow path (22) through which the air is flowed from an outside into an inside of the vessel body (7); a discharge part (16) provided in the opening (8) and having an outflow path (26) through which the air is discharged from the inside to the outside of the vessel body (7); a discharge electrode (15) provided in the inside of the vessel body (7) and to which a high voltage is applied; and a medium storage part (50) provided in the inside of the vessel body (7) and capable of storing a medium for collecting the particles in the air charged by the discharge electrode (15).
    Type: Application
    Filed: September 13, 2021
    Publication date: November 9, 2023
    Applicant: AMANO CORPORATION
    Inventors: Kyohei FUKUDA, Akira MIZUNO, Shinjirou KATSUSHIMA, Kouichi KITABAYASHI, Yuji MAKISHIMA
  • Publication number: 20230320640
    Abstract: A determination device includes an acquisition unit, a first determination unit, a second determination unit, and an output unit. The acquisition unit is configured to acquire a sightline direction of a user and a sightline direction of at least one facing person facing the user. The first determination unit is configured to determine whether a sightline of the user is directed to the facing person based on the sightline direction of the user acquired by the acquisition unit. The second determination unit is configured to determine whether a sightline of the facing person is directed to the user based on the sightline direction of the facing person acquired by the acquisition unit. The output unit is configured to output a feedback to the user and/or an executor based on a result of a determination of the first determination unit and a result of a determination of the second determination unit.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 12, 2023
    Applicants: NATIONAL UNIVERSITY CORPORATION CHIBA UNIVERSITY, Sumitomo Pharma Co., Ltd.
    Inventors: Toshiya NAKAGUCHI, Kyohei FUKUDA, Eiji SHIMIZU, Yoshiyuki HIRANO, Naomi SHIRAIWA, Yuki IKEDA, Masanori MIYAUCHI
  • Publication number: 20220385801
    Abstract: An apparatus includes a first operation member, an assigning unit configured to assign one of a plurality of functions to the first operation member, and a second operation member configured to enable a user to provide a setting relating to a specific function among the plurality of functions. The assigning unit assigns the specific function to the first operation member according to an operation of the second operation member.
    Type: Application
    Filed: May 20, 2022
    Publication date: December 1, 2022
    Inventor: Kyohei Fukuda
  • Patent number: 10109603
    Abstract: A semiconductor device includes semiconductor elements and a multilayer substrate including an insulating plate and a circuit board on which the semiconductor elements are arranged that is arranged on the front surface of the insulating plate. The semiconductor device also includes a printed circuit board that is arranged facing a principal surface of the multilayer substrate and in which through holes are formed, as well as conductive posts that are inserted through the through holes and are electrically connected to the semiconductor elements via bonding materials. Furthermore, the semiconductor device includes fuses that are formed between the interior walls of the through holes and the outer peripheral surfaces of the conductive posts, are electrically connected to the printed circuit board via the conductive posts, and melt at a first temperature.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 23, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tatsuo Nishizawa, Kyohei Fukuda
  • Patent number: 9824950
    Abstract: A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front surface of the insulating plate, and a radiator plate that is fixed to a rear surface of the insulating plate, a semiconductor chip that is fixed to the circuit pattern, an external lead terminal that is connected to a surface electrode of the semiconductor chip through a wiring line, a molding resin that covers the insulating substrate, the semiconductor chip, the wiring line, and the external lead terminal such that a rear surface of the radiator plate and a portion of the external lead terminal are exposed, and an anchor layer including a stripe-shaped concave portion which is formed in the circuit pattern by laser beam irradiation.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: November 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kyohei Fukuda, Tatsuo Nishizawa, Yuhei Nishida, Eiji Mochizuki
  • Publication number: 20170271280
    Abstract: A semiconductor device includes semiconductor elements and a multilayer substrate including an insulating plate and a circuit board on which the semiconductor elements are arranged that is arranged on the front surface of the insulating plate. The semiconductor device also includes a printed circuit board that is arranged facing a principal surface of the multilayer substrate and in which through holes are formed, as well as conductive posts that are inserted through the through holes and are electrically connected to the semiconductor elements via bonding materials. Furthermore, the semiconductor device includes fuses that are formed between the interior walls of the through holes and the outer peripheral surfaces of the conductive posts, are electrically connected to the printed circuit board via the conductive posts, and melt at a first temperature.
    Type: Application
    Filed: February 10, 2017
    Publication date: September 21, 2017
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Tatsuo NISHIZAWA, Kyohei FUKUDA
  • Patent number: 9622351
    Abstract: It is aimed to reduce the electrical field intensity at a laminate substrate on which a semiconductor device is placed. A semiconductor module includes a laminate substrate including an insulative plate, a circuit board provided on a first surface of the insulative plate and a metal plate provided on a second surface that is opposite to the first surface, and an interconnecting substrate that is provided so as to oppose the laminate substrate and that includes a metal layer. Here, the insulative plate extends more outside than an outer edge portion of the circuit board, and the metal layer has a region overlapping the outer edge portion of the circuit board and extends more outside than the outer edge portion of the circuit board.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 11, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kyohei Fukuda
  • Publication number: 20160295701
    Abstract: It is aimed to reduce the electrical field intensity at a laminate substrate on which a semiconductor device is placed. A semiconductor module includes a laminate substrate including an insulative plate, a circuit board provided on a first surface of the insulative plate and a metal plate provided on a second surface that is opposite to the first surface, and an interconnecting substrate that is provided so as to oppose the laminate substrate and that includes a metal layer. Here, the insulative plate extends more outside than an outer edge portion of the circuit board, and the metal layer has a region overlapping the outer edge portion of the circuit board and extends more outside than the outer edge portion of the circuit board.
    Type: Application
    Filed: March 3, 2016
    Publication date: October 6, 2016
    Inventor: Kyohei FUKUDA
  • Patent number: 9305910
    Abstract: A semiconductor device includes an insulating substrate having a first conductive pattern on a first insulating substrate; a first semiconductor element having one surface fixed to the first conductive pattern; a printed circuit board having a conductive layer on a second insulating substrate and a plurality of metal pins fixed to the conductive layer; and a third insulating substrate. A portion of pins constituting the metal pins is fixed to other surface of the first semiconductor element, and the printed circuit board with the metal pins is sandwiched between the insulating substrate having the first conductive pattern and the third insulating substrate.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 5, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masafumi Horio, Kyohei Fukuda, Motohito Hori, Yoshinari Ikeda
  • Publication number: 20150243640
    Abstract: A semiconductor device includes an insulating substrate having a first conductive pattern on a first insulating substrate; a first semiconductor element having one surface fixed to the first conductive pattern; a printed circuit board having a conductive layer on a second insulating substrate and a plurality of metal pins fixed to the conductive layer; and a third insulating substrate. A portion of pins constituting the metal pins is fixed to other surface of the first semiconductor element, and the printed circuit board with the metal pins is sandwiched between the insulating substrate having the first conductive pattern and the third insulating substrate.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 27, 2015
    Inventors: Masafumi HORIO, Kyohei FUKUDA, Motohito HORI, Yoshinari IKEDA
  • Publication number: 20150187671
    Abstract: A semiconductor device according to the invention includes an insulating substrate including an insulating plate, a circuit pattern that is formed on a front surface of the insulating plate, and a radiator plate that is fixed to a rear surface of the insulating plate, a semiconductor chip that is fixed to the circuit pattern, an external lead terminal that is connected to a surface electrode of the semiconductor chip through a wiring line, a molding resin that covers the insulating substrate, the semiconductor chip, the wiring line, and the external lead terminal such that a rear surface of the radiator plate and a portion of the external lead terminal are exposed, and an anchor layer including a stripe-shaped concave portion which is formed in the circuit pattern by laser beam irradiation.
    Type: Application
    Filed: March 12, 2015
    Publication date: July 2, 2015
    Inventors: Kyohei FUKUDA, Tatsuo NISHIZAWA, Yuhei NISHIDA, Eiji MOCHIZUKI
  • Patent number: 9059009
    Abstract: Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips.
    Type: Grant
    Filed: December 25, 2012
    Date of Patent: June 16, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masafumi Horio, Kyohei Fukuda, Motohito Hori, Yoshinari Ikeda
  • Publication number: 20140346676
    Abstract: Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces, formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips.
    Type: Application
    Filed: December 25, 2012
    Publication date: November 27, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masafumi Horio, Kyohei Fukuda, Motohito Hori, Yoshinari Ikeda
  • Patent number: 8748225
    Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: June 10, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kyohei Fukuda, Eiji Mochizuki, Mitsutoshi Sawano, Takaaki Suzawa
  • Patent number: 8710674
    Abstract: Aspects of the invention provide an internal wiring structure of a power semiconductor device, which is capable of reducing a mutual inductance between two wiring conductors and improving the heat dissipation effect, the two wiring conductors being disposed so as to oppose each other and having currents flowing in the same direction. In some aspects, notches can be formed alternately from side walls of two flat plates, on the flat plates, to obtain two wiring conductors. The two wiring conductors can be disposed so as to oppose each other and in parallel to each other so that currents flow along the notches in directions opposite to each other. Accordingly, in some circumstances, the mutual inductance can be reduced. Further, in some circumstances, the dimensions of the planes of the wiring conductors obtained by forming the notches can be increased to improve the heat dissipation.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: April 29, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Kyohei Fukuda
  • Patent number: 8692350
    Abstract: A semiconductor device, and method of manufacturing the device, having a p type diffusion layer; a V-groove including a bottom surface parallel to the rear surface and exposing the p type diffusion layer and a tapered side surface rising from the bottom surface; a p type semiconductor layer on the rear surface surrounded by the tapered side surface of the V-groove; and a p type isolation layer formed on the side surface and electrically connecting the p type diffusion layer on the front surface and the p type semiconductor layer on the rear surface. The V-groove has a chamfered configuration around the intersection between a corner part of the side surface and the bottom surface of the V-groove. An object is to prevent performance degradation due to stress concentration at the corner part of a recessed part caused by thermal history in soldering.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 8, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Takahito Harada, Fumio Shigeta, Kyohei Fukuda
  • Patent number: 8598688
    Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: December 3, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kyohei Fukuda, Eiji Mochizuki, Mitsutoshi Sawano, Takaaki Suzawa
  • Publication number: 20130277849
    Abstract: Aspects of the invention provide an internal wiring structure of a power semiconductor device, which is capable of reducing a mutual inductance between two wiring conductors and improving the heat dissipation effect, the two wiring conductors being disposed so as to oppose each other and having currents flowing in the same direction. In some aspects, notches can be formed alternately from side walls of two flat plates, on the flat plates, to obtain two wiring conductors. The two wiring conductors can be disposed so as to oppose each other and in parallel to each other so that currents flow along the notches in directions opposite to each other. Accordingly, in some circumstances, the mutual inductance can be reduced. Further, in some circumstances, the dimensions of the planes of the wiring conductors obtained by forming the notches can be increased to improve the heat dissipation.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 24, 2013
    Inventor: Kyohei FUKUDA
  • Publication number: 20130237016
    Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.
    Type: Application
    Filed: April 10, 2013
    Publication date: September 12, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kyohei FUKUDA, Eiji MOCHIZUKI, Mitsutoshi SAWANO, Takaaki SUZAWA