Patents by Inventor Kyohei Sakajiri
Kyohei Sakajiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230408901Abstract: Aspects of the disclosed technology relate to techniques for applying optical proximity correction to free form shapes. Each optical proximity correction iteration comprises: computing edge adjustment values for the straight ty correction iteration immediately preceding the each of the plurality of optical proximity correction iterations, adjusting locations of the straight line fragments based on the determined edge adjustment values, determining smooth boundary lines for the layout features based on the straight line fragments on the adjusted locations, performing a simulation process on the layout features having the smooth boundary lines to determine a simulated image of the layout features, and deriving the edge adjustment errors for the straight line fragments based on comparing the simulated image with a target image of the layout features.Type: ApplicationFiled: October 8, 2020Publication date: December 21, 2023Inventors: George P. Lippincott, Vladislav Liubich, Kyohei Sakajiri
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Publication number: 20170262570Abstract: Geometric elements within regions needing lithographic repair are examined to identify characteristics of the patterns formed by those geometric elements. Repair regions with common pattern characteristics then are categorized into classes. When a repair solution is determined for a selected repair region, that repair solution is applied to the other repair regions in the same class as the selected repair region. In some implementations, the repair solution is applied to every instance of a repair region within the class. With still other implementations, the hierarchy of the layout design is examined to determine a hierarchical cell that includes all of the design elements of the selected repair region. The repair solution can then be applied to the design elements within that cell, propagating the repair throughout the design.Type: ApplicationFiled: March 11, 2016Publication date: September 14, 2017Inventor: Kyohei Sakajiri
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Publication number: 20150143323Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Juan Andres Torres Robles, Yuri Granik, Kyohei Sakajiri
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Patent number: 9032357Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.Type: GrantFiled: November 18, 2013Date of Patent: May 12, 2015Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, Yuri Granik, Kyohei Sakajiri
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Patent number: 8713487Abstract: After layout design data has been modified using a resolution enhancement process, a repair flow is initiated. This repair flow includes checking a layout design altered by a resolution enhancement process for errors. A repair process is performed to correct detected sub-resolution assist feature errors. The repair process may employ a rule-based sub-resolution assist feature technique, a model-based sub-resolution assist feature technique, an inverse lithography-based sub-resolution assist feature technique, or any combination thereof.Type: GrantFiled: January 9, 2013Date of Patent: April 29, 2014Assignee: Mentor Graphics CorporationInventors: James Word, Kyohei Sakajiri
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Patent number: 8713488Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, context and visible portions. An inverse lithography process is then performed on the core portion of the re-correction region while taking into account effects from the context portion of the re-correction region to generate a first modified re-correction region. A traditional OPC process is then performed on the core and context portions of the first modified re-correction region while taking into account effects from the visible portion of the first modified re-correction region to generate a second modified re-correction region.Type: GrantFiled: January 14, 2013Date of Patent: April 29, 2014Assignee: Mentor Graphics CorporationInventor: Kyohei Sakajiri
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Patent number: 8510686Abstract: Various implementations of the invention provide for generation of a high transmission phase shift mask layout through inverse lithography techniques. In various implementations of the present invention, a set of mask data having a plurality of pixels is generated. The transmission value associated with each pixel may then be determined through an inverse lithography technique. With various implementations of the invention, the inverse lithography technique identifies an objective function, minimizes the objective function in relation to a simulation of the optical lithographic process, such that the transmission value, which is greater than 6%, may be determined.Type: GrantFiled: September 30, 2011Date of Patent: August 13, 2013Assignee: IMECInventors: Eric Henri Jan Hendrickx, Alexander V. Tritchkov, Kyohei Sakajiri
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Patent number: 8302039Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.Type: GrantFiled: April 12, 2010Date of Patent: October 30, 2012Assignee: Mentor Graphics CorporationInventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd
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Patent number: 8234598Abstract: Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by proximity correction.Type: GrantFiled: October 27, 2011Date of Patent: July 31, 2012Inventors: Yuri Granik, Kyohei Sakajiri
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Publication number: 20120042291Abstract: Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by proximity correction.Type: ApplicationFiled: October 27, 2011Publication date: February 16, 2012Inventors: Yuri Granik, Kyohei Sakajiri
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Patent number: 7987434Abstract: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer.Type: GrantFiled: January 23, 2009Date of Patent: July 26, 2011Assignee: Mentor Graphics CorporationInventors: Yuri Granik, Kyohei Sakajiri
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Publication number: 20110004856Abstract: Various implementations of the invention provide for the generation of “smooth” mask contours by inverse mask transmission derivation and by subsequently “smoothing” the derived mask contours by proximity correction.Type: ApplicationFiled: February 22, 2010Publication date: January 6, 2011Inventors: Yuri Granik, Kyohei Sakajiri
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Publication number: 20100216061Abstract: Various implementations of the invention provide for generation of a high transmission phase shift mask layout through inverse lithography techniques. In various implementations of the present invention, a set of mask data having a plurality of pixels is generated. The transmission value associated with each pixel may then be determined through an inverse lithography technique. With various implementations of the invention, the inverse lithography technique identifies an objective function, minimizes the objective function in relation to a simulation of the optical lithographic process, such that the transmission value, which is greater than 6%, may be determined.Type: ApplicationFiled: March 31, 2009Publication date: August 26, 2010Inventors: Eric Henri Jan Hendrickx, Alexander V. Tritchkov, Kyohei Sakajiri
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Publication number: 20100199107Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.Type: ApplicationFiled: April 12, 2010Publication date: August 5, 2010Inventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd
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Patent number: 7698664Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.Type: GrantFiled: May 21, 2007Date of Patent: April 13, 2010Inventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd
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Patent number: 7552416Abstract: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer.Type: GrantFiled: January 8, 2007Date of Patent: June 23, 2009Inventors: Yuri Granik, Kyohei Sakajiri
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Publication number: 20090125869Abstract: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer.Type: ApplicationFiled: January 23, 2009Publication date: May 14, 2009Inventors: Yuri Granik, Kyohei Sakajiri
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Publication number: 20080148348Abstract: Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses).Type: ApplicationFiled: February 25, 2008Publication date: June 19, 2008Inventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd
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Patent number: 7353468Abstract: Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses).Type: GrantFiled: August 17, 2004Date of Patent: April 1, 2008Inventors: John G. Ferguson, Fedor G. Pikus, Kyohei Sakajiri, Laurence W. Grodd
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Publication number: 20070266445Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.Type: ApplicationFiled: May 21, 2007Publication date: November 15, 2007Inventors: John Ferguson, Fedor Pikus, Kyohei Sakajiri, Laurence Grodd