Abstract: A system for calculating mask data to create a desired layout pattern on a wafer reads all or a portion of a desired layout pattern. Mask data having pixels with transmission values is defined along with corresponding optimal mask data pixel transmission values. An objective function is defined that compares image intensities as would be generated on a wafer with an optimal image intensity at a point corresponding to a pixel. The objective function is minimized to determine the transmission values of the mask pixels that will reproduce the desired layout pattern on a wafer.

Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.

Abstract: The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification of the location of the edge segments may conditionally occur. Additionally, if these modifications occur, a method to minimize the introduction of short edges during the modification is provided.

Abstract: Electronic data can be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information can be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool can be used to secure the information. A system can then unlock and use the secured information without revealing the same. In one desirable aspect, information can be encrypted or decrypted using a key, the key being generated based on licensing information associated with a software application.

Abstract: Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be processed without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. In one aspect, such access or secure use of the information may depend on one or more conditions being met (e.g., a time period or a number of uses or accesses).

Abstract: Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same.

Abstract: The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification of the location of the edge segments may conditionally occur. Additionally, if these modifications occur, a method to minimize the introduction of short edges during the modification is provided.

Abstract: The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification of the location of the edge segments may conditionally occur. Additionally, if these modifications occur, a method to minimize the introduction of short edges during the modification is provided.

Abstract: The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification of the location of the edge segments may conditionally occur. Additionally, if these modifications occur, a method to minimize the introduction of short edges during the modification is provided.

Abstract: The invention discloses a method and apparatus for modifying, as appropriate, the geometries of a polygon. Based on various attributes associated with the polygon and its surroundings, modification of the location of the edge segments may conditionally occur. Additionally, if these modifications occur, a method to minimize the introduction of short edges during the modification is provided.

Abstract: A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process.

Abstract: A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process.

Abstract: A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process.