Abstract: A semiconductor memory incorporates a protecting circuit which causes data, stored in a memory portion, to be output by executing a key canceling sequence from an external apparatus. The data stored in the memory are output only when a key canceling signal is input to the protecting circuit. Thus the data are not output only by inputting an address signal and a reading signal to the memory apparatus. As a result, it is impossible to find out the contents of the program stored in the memory portion without inputting the key canceling signal.

Abstract: A color encoder is incorporated in an apparatus for reproducing a signal recorded on a disk for a video-CD, CD-G, or similar system. The color encoder serves as an interface between such an apparatus and a television receiver. The color encoder has a color-difference signal forming circuit for forming a color-difference signal from R, G, and B signals reproduced from a disk, a modulation circuit for modulating a chrominance subcarrier with the color-difference signal, and chrominance subcarrier generating device for generating the chrominance subcarrier. Moreover, to generate a chrominance signal having the same frequency for any of a plurality of clocks having different predetermined frequencies, the chrominance subcarrier generating device has a plurality of ROMs, each containing in its data area a data table corresponding to a different frequency, and a ROM switching circuit for selecting a ROM to be accessed from among the plurality of ROMs in accordance with a switching signal.

Abstract: A color encoder is incorporated in an apparatus for reproducing a signal recorded on a disk for a video-CD, CD-G, or similar system. The color encoder serves as an interface between such an apparatus and a television receiver. The color encoder converts R, G, and B signals reproduced from a disk into a color television signal. The color encoder is provided with a circuit for generating a blanking interval control signal that is used to switch between blanking intervals of different duration in accordance with a select signal, so that the duration of the time interval during which video signals are suppressed can be selectively varied. The color encoder has, in the input paths for the R, G, and B signals, switches for enabling and disabling the passage of those signals, and these switches are controlled by the blanking control signal.

Abstract: An encoder has a function of converting received digital RGB signals into analog television signals and a function of displaying on-screen displays. An internal chrominance signal generating section is driven and controlled by subsidiary display data supplied from outside via a subsidiary display data input terminal to output digital subsidiary display chrominance signals. A multiplexer selects and alternatively outputs either received main display signals or subsidiary display chrominance signals from the internal signal generating section. Switching of the multiplexer is controlled by a switching signal that is supplied from outside via a terminal.

Abstract: An encoder converts digital RGB signals into analog television signals. This encoder forms digital composite, luminance and chrominance signals based on digital signals input through an RGB input terminal. The encoder has a first, a second and a third D/A converters for converting digital composite, luminance and chrominance signals into corresponding analog signals. The encoder is provided with a switch for activating required ones of the three D/A converters and deactivating others of the D/A converters.

Abstract: An IC according to the present invention contains a counter, which includes a plurality of incomplete coincidence detection circuits each associated with a different one of a corresponding number of flip-flops storing respective bit data of an aimed value, each incomplete coincidence detection circuit including a first logic element for receiving a Q or Q output of said associated flip-flop and a one-bit output from a bit location of the counter corresponding to the different flip-flop, and a second logic element for receiving an output of the first logic element and the other of the Q and Q output of the different flip-flop to provide a coincidence detection signal, the detection circuit being adapted to detect a coincidence of the aimed value with the count value when all of the incomplete coincidence detection circuits output the coincidence detection signals.