Abstract: A self-refresh circuit included in a semiconductor integrated circuit includes a ring oscillator, a double period counter, an SELF generating portion generating a signal SELF0 corresponding to an internal RAS, and a BBUE generating portion. The double period counter performs a count operation, using the output signal of the double period counter as a basic signal. The BBUE generating portion generates a BBUE signal in accordance with the output of double period counter. When the BBUE rises to H-level, the self-refresh signal SELF corresponding to signal SELF0 is issued. A layout area can be small, and timing of entry in a self-refresh mode can be finely set.

Abstract: A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

Abstract: A self-refresh circuit included in a semiconductor integrated circuit includes a ring oscillator, a double period counter, an SELF generating portion generating a signal SELFO corresponding to an internal RAS, and a BBUE generating portion. The double period counter performs a count operation, using the output signal of the double period counter as a basic signal. The BBUE generating portion generates a BBUE signal in accordance with the output of double period counter. When the BBUE rises to H-level, the self-refresh signal SELF corresponding to signal SELF0 is issued. A layout area can be small, and timing of entry in a self-refresh mode can be finely set.

Abstract: A VPP generation circuit included in the inventive semiconductor integrated circuit includes a VPP dividing circuit dividing a step-up voltage VPP, a VDDA dividing circuit dividing an array voltage VDDA supplied to a memory cell array area, a VREFD generation circuit generating a reference voltage VREFD on the basis of an output of the VDDA dividing circuit and a comparator part comparing the reference voltage VREFD with a voltage VPPn output from the VPP dividing circuit. Thus, the step-up voltage VPP can be changed in response to change of the array voltage VDDA.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial parallel conversion circuits subjecting received, packetized data to serial parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: In a circuit in which a step-up potential is generated by a charge pump, a through current passing through a buffer circuit (161bb) when an activation signal (ACTL) is at its low level, can be reduced by arranging so that a detector (161ca) is ahead of another detector (161ba) in detecting a decrease in step-up potential VPP.

Abstract: A semiconductor memory device includes an output control signal generation circuit for generating an output control signal to designate initiation of data output according to an external control signal, and a boosting circuit boosting an external power supply voltage. Each of the plurality of output control circuits generates an output permit signal with the output level of the boosting circuit as the activation level in response to activation of an output control signal. The output permit signals are transmitted to a plurality of output circuits by a corresponding one of a plurality of signal lines. Each of the plurality of output circuits drives the potential of a corresponding output terminal according to a read out data signal and an output permit signal.

Abstract: A packaging structure is capable of electrically connecting an external lead to a pad of a semiconductor chip by directly bonding the external lead to the pad of the semiconductor chip without an adhesive, which requires no resin sealing. The packaging structure comprises a lead member 20 having an fitting part with a U-shaped cross section, which can be fit into the semiconductor chip 10 from the end part thereof, and the fitting part pinches the semiconductor chip by means of an elastic restoration force or a plastic deformation, thereby allowing a contact point 20a at one end of the lead member 20 to directly bring into contact with the pad part 11 of the semiconductor chip and, at the same time, the fitting part is provided with a construction for insulating the lead member from the semiconductor chip in the internal circumference except for the contact point.

Abstract: A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power supply interconnection, above the first interconnection, applies a second potential to the gate of the transistor. A third power supply interconnection is formed above, in parallel with and connected to the second power supply interconnection. An externally sourced potential is down-converted to be applied appropriately to the first, second and third power supply interconnections. This configuration achieves a semiconductor device that is less susceptible to power supply noise.

Abstract: A row address signal output from an internal row address generation circuit according to an output from a ring oscillator activated in response to an externally applied burn-in mode designation signal SBT, is scrambled by an operation circuit and then applied to a row decoder. Meanwhile, a signal output from a data output circuit in response to activation of signal SBT is scrambled by a data scrambler and checker pattern data is applied to a memory cell array such that it corresponds to a physical address of the memory cell array.

Abstract: A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.

Abstract: A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

Abstract: A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power supply interconnection, above the first interconnection, applies a second potential to the gate of the transistor. A third power supply interconnection is formed above, in parallel with and connected to the second power supply interconnection. An externally sourced potential is down-converted to be applied appropriately to the first, second and third power supply interconnections. This configuration achieves a semiconductor device that is less susceptible to power supply noise.

Abstract: A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

Abstract: A plurality of internal power supply voltage generating circuits generate internal power supply voltages. A column select signal at the same voltage level as a first internal power supply voltage applied to a sense amplifier is generated to an I/O gate circuit connecting a bit line pair and an internal data line pair together. A current driving capability of an I/O gate circuit is made relatively small, so that rapid change in potential on a sense node of a sense amplifier is prevented. Thereby, inversion of latched data of the sense amplifier due to collision of data is prevented in such a case voltages on the internal data line pair are not equalized sufficiently.

Abstract: A lead frame of a DRAM chip includes a base end portion to which an external power supply potential ext.cndot.VCC is applied, and two branch portions branching away from the base end portion. A tip portion of one of these two branch portions is connected to an output buffer, and a tip portion of the other is connected to another circuit. Power supply noise generated at the output buffer passes through one of the branch portions to the outside, and will never reach another circuit through the other branch portion. Accordingly, a DRAM which is less susceptible to power supply noise can be provided.

Abstract: A current source is provided between a first p channel MOS transistor and a ground node, and a current/voltage converting element is provided isolatedly from the current source between the ground node and a second p channel MOS transistor having a conductance coefficient sufficiently larger than that of the first MOS transistor. The second MOS transistor is connected through a resistive element to an external power supply node. A voltage produced by the current/voltage converting element is converted into current by a voltage/current converting portion. Thus, constant current free from both vibration and a deadlock phenomenon and with small external power supply voltage dependency is supplied.

Abstract: A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.