Patents by Inventor Kyoji Yamasaki

Kyoji Yamasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit for decreasing current consumption in data output circuit in case one of two supply voltages fails
    Patent number: 5291454
    Abstract: An improved output buffer circuit applicable to dynamic random access memories (DRAms) is disclosed. First power supply voltage Vcc1 is supplied to a conventional output main amplifier 3ai. Second power supply voltage Vcc2 is supplied to output driver circuit 4i. Potential fixing circuit 3bi operated in response to power supply failure detecting signal PFR of first power supply voltage Vcc1 is connected to the output of output main amplifier circuit 3ai. When second power supply voltage Vcc2 is applied without first power supply voltage Vcc1 being supplied, the gates of driving transistors Q1 and Q2 are fixed to ground potential in response to the signal PFR. Consequently, undesired current consumption is avoided, since a penetrating current does not flow through transistors Q1 and Q2.
    Type: Grant
    Filed: January 23, 1992
    Date of Patent: March 1, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kyoji Yamasaki, Yutaka Ikeda