Patents by Inventor Kyoji Yamashita

Kyoji Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140043467
    Abstract: According to one embodiment, a defect inspection apparatus includes an inspection unit configured to acquire a plurality of inspection images by photographing repetitive patterns of not larger than a resolution limit of an optical system under different optical conditions with respect to a to-be-inspected sample, an edge image extraction unit configured to respectively extract edge images from the plural inspection images, and a defect determination unit configured to determine the presence of a defect of the pattern based on the plural edge images.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 13, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kyoji YAMASHITA
  • Patent number: 8260031
    Abstract: A pattern inspection apparatus includes a magnification conversion unit to convert first sample optical image data to higher resolution second sample optical image data, a low-pass filter configured to filter first design image data which has a resolution N times that of the first sample optical image data, an optical filter which calculates third design image data by convolving the second design image data with an optical model function, a coefficient acquisition unit configured to acquire a coefficient of the predetermined optical model function using the second sample optical image data and the third design image data, an optical image acquisition unit configured to acquire actual optical image data of an inspection target workpiece, a reference image data generation unit configured to generate reference image data corresponding to the actual optical image data, and a comparison unit configured to compare the actual optical image data with the reference image data.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: September 4, 2012
    Assignees: Kabushiki Kaisha Toshiba, NEC Corporation
    Inventor: Kyoji Yamashita
  • Patent number: 8233698
    Abstract: A pattern inspection apparatus includes a first unit configured to acquire an optical image of a target workpiece to be inspected, a second unit configured to generate a reference image to be compared, a third unit configured, by using a mathematical model in which a parallel shift amount, an expansion and contraction error coefficient, a rotation error coefficient, a gray-level offset and an image transmission loss ratio are parameters, to calculate each of the parameters by a least-squares method, a forth unit configured to generate a corrected image by shifting a position of the reference image by a displacement amount, based on the each of the parameters, and a fifth unit configured to compare the corrected image with the optical image.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: July 31, 2012
    Assignees: Kabushiki Kaisha Toshiba, NEC Corporation
    Inventor: Kyoji Yamashita
  • Patent number: 8013361
    Abstract: Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: September 6, 2011
    Assignee: Panasonic Corporation
    Inventors: Kyoji Yamashita, Katsuhiro Otani, Katsuya Arai, Daisaku Ikoma
  • Patent number: 7809181
    Abstract: A pattern inspection apparatus includes a first unit configured to acquire an optical image of pattern, a second unit configured to generate a reference image to be compared, a third unit configured to calculate elements of a normal matrix for a least-squares method for calculating a displacement amount displaced from a preliminary alignment position, a forth unit configured to estimate a type of the reference image pattern, by using some of the elements of the normal matrix, a fifth unit configured to calculate the displacement amount based on the least-squares method, by using a normal matrix obtained by deleting predetermined elements depending upon the type of the pattern, a sixth unit configured to correct an alignment position between the optical image and the reference image to a position displaced by the displacement amount, and a seventh unit configured to compare the optical image and the reference image.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: October 5, 2010
    Assignee: Advanced Mask Inspection Technology Inc.
    Inventor: Kyoji Yamashita
  • Patent number: 7792663
    Abstract: A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Daisaku Ikoma, Kyoji Yamashita, Yasuyuki Sahara, Katsuhiro Ootani, Tomoyuki Ishizu
  • Patent number: 7709900
    Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: May 4, 2010
    Assignee: Panasonic Corporation
    Inventors: Daisaku Ikoma, Atsuhiro Kajiya, Katsuhiro Ootani, Kyoji Yamashita
  • Patent number: 7655904
    Abstract: A target workpiece inspection apparatus comprises an optical image acquiring unit to acquire an optical image of a target workpiece, a reference image generating unit to generate a reference image to be compared, a difference judging unit to judge whether an absolute value of difference between pixel values of the images in each pixel at a preliminary alignment position between the images is smaller than a threshold value, a least-squares method displacement calculating unit to calculate a displacement amount displaced from the preliminary alignment position, by using a regular matrix for a least-squares method obtained from a result judged, a position correcting unit to correct an alignment position between the optical image and the reference image to a position displaced from the preliminary alignment position by the displacement amount, and a comparing unit to compare the optical image and the reference image whose alignment position has been corrected.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: February 2, 2010
    Assignee: Advanced Mask Inspection Technology Inc.
    Inventor: Kyoji Yamashita
  • Publication number: 20090238441
    Abstract: A pattern inspection apparatus includes a magnification conversion unit configured to input first sample optical image data, and to convert the first sample optical image data to second sample optical image data which has a resolution N times that of the first sample optical image data, a low-pass filter configured to input first design image data which has a resolution N times that of the first sample optical image data and in which a gray level value corresponding to the first sample optical image data is defined, and to calculate second design image data by convolving the first design image data with a predetermined low-pass filtering function, an optical filter configured to calculate third design image data by convolving the second design image data with a predetermined optical model function, a coefficient acquisition unit configured to acquire a coefficient of the predetermined optical model function by performing a predetermined calculation by using the second sample optical image data and the third d
    Type: Application
    Filed: December 31, 2008
    Publication date: September 24, 2009
    Applicant: Advanced Mask Inspection Technology, Inc.
    Inventor: Kyoji YAMASHITA
  • Patent number: 7577288
    Abstract: A sample inspection apparatus according to an aspect of the present invention includes a first SSD calculating unit which calculates the displacement amount from a preliminary alignment position of an optical image and a reference image to a position where the SSD of a pixel value of the optical image and a pixel value of the reference image is minimized, and a least-square method calculating unit which calculates the displacement amount by a least-square method from the preliminary alignment position of the optical image and the reference image, wherein the alignment position of the optical image and the reference image is corrected to a position where the smaller SSD of the minimum SSD obtained as the result of the calculation by the first SSD calculating unit and the SSD obtained as the result of the calculation by the determined by the least-square method calculating unit is obtained.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: August 18, 2009
    Assignee: Advanced Mask Inspection Technology Inc.
    Inventor: Kyoji Yamashita
  • Patent number: 7562327
    Abstract: In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: July 14, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinsaku Sekido, Kyoji Yamashita, Katsuhiro Ootani, Yasuyuki Sahara, Daisaku Ikoma
  • Patent number: 7551767
    Abstract: A pattern inspection apparatus uses a die-to-database comparison method which compares detected pattern data obtained from an optical image of a pattern of a plate to be inspected with first reference pattern data obtained from designed pattern data in combination with a die-to-die comparison method which compares the detected pattern data with second reference pattern data obtained by detecting an area to be a basis for repetition. A computer detects presence of a plurality of repeated pattern areas from layout information contained in the designed pattern data, reads the arrangement, the number, the dimension and the repeated pitch of the repeated pattern areas, and automatically fetches an inspection area of the die-to-die comparison method.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: June 23, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Tsuchiya, Kyoji Yamashita, Toshiyuki Watanabe, Ikunao Isomura, Toru Tojo, Yasushi Sanada
  • Patent number: 7519593
    Abstract: A data searching unit 12 of a data searching apparatus 10 Obtains, according to a searching request including a search condition specified by a data searching application 16, metadata which satisfy the search condition from a data storage unit 11, and instructs an external communication unit 15 to request searching of data to a data providing apparatus 20 with the same search condition.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: April 14, 2009
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventors: Kazuko Abe, Junichi Yamamoto, Rei Yano, Masataka Yamada, Yasuhide Kurosaki, Michiyo Ikegami, Kyoji Yamashita, Kouji Gouda
  • Patent number: 7476957
    Abstract: An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 13, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinji Watanabe, Daisaku Ikoma, Kyoji Yamashita, Katsuhiro Ootani
  • Publication number: 20080283922
    Abstract: A semiconductor device includes a first conductivity type well formed on a semiconductor substrate, and a first transistor and a second transistor formed on the well. The first transistor has first pocket regions containing a first conductivity type impurity and first source/drain regions containing a second conductivity type impurity, and the second transistor has second pocket regions containing a first conductivity type impurity and second source/drain regions containing a second conductivity type impurity, and executes an analog function. A concentration of the first conductivity type impurity contained in the source-side and the drain-side second pocket regions is lower than a concentration of the first conductivity type impurity included in the first pocket regions.
    Type: Application
    Filed: January 28, 2008
    Publication date: November 20, 2008
    Inventors: Kyoji YAMASHITA, Daisaku IKOMA
  • Publication number: 20080260234
    Abstract: A pattern inspection apparatus includes a first unit configured to acquire an optical image of a target workpiece to be inspected, a second unit configured to generate a reference image to be compared, a third unit configured, by using a mathematical model in which a parallel shift amount, an expansion and contraction error coefficient, a rotation error coefficient, a gray-level offset and an image transmission loss ratio are parameters, to calculate each of the parameters by a least-squares method, a forth unit configured to generate a corrected image by shifting a position of the reference image by a displacement amount, based on the each of the parameters, and a fifth unit configured to compare the corrected image with the optical image.
    Type: Application
    Filed: January 9, 2008
    Publication date: October 23, 2008
    Applicant: Advanced Mask Inspection Technology
    Inventor: Kyoji YAMASHITA
  • Patent number: 7421109
    Abstract: A pattern inspecting method, comprising preparing a sample having a first and a second inspection regions and an imaging device having a plurality of pixels, scanning the first inspection region to a first direction using the imaging device to obtain a first measurement pattern representing at least parts of the first inspection region, scanning the second inspection region to the first direction using the imaging device to obtain a second measurement pattern representing at least parts of the second inspection region, comparing the first measurement pattern and the second measurement pattern with each other to determine presence or absence of a defect formed on the sample, and controlling a scanning condition for scanning a pattern of the second inspection region by the imaging device so as to keep the same with the scanning condition when the pattern of the first inspection region is scanned by the imaging device.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: September 2, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Tsuchiya, Kyoji Yamashita, Toshiyuki Watanabe, Ikunao Isomura, Toru Tojo, Yasushi Sanada
  • Patent number: 7415149
    Abstract: A pattern inspection apparatus uses a die-to-database comparison method which compares detected pattern data obtained from an optical image of a pattern of a plate to be inspected with first reference pattern data obtained from designed pattern data in combination with a die-to-die comparison method which compares the detected pattern data with second reference pattern data obtained by detecting an area to be a basis for repetition. A computer detects presence of a plurality of repeated pattern areas from layout information contained in the designed pattern data, reads the arrangement, the number, the dimension and the repeated pitch of the repeated pattern areas, and automatically fetches an inspection area of the die-to-die comparison method.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Tsuchiya, Kyoji Yamashita, Toshiyuki Watanabe, Ikunao Isomura, Toru Tojo, Yasushi Sanada
  • Publication number: 20080166054
    Abstract: A pattern inspection apparatus uses a die-to-database comparison method which compares detected pattern data obtained from an optical image of a pattern of a plate to be inspected with first reference pattern data obtained from designed pattern data in combination with a die-to-die comparison method which compares the detected pattern data with second reference pattern data obtained by detecting an area to be a basis for repetition. A computer detects presence of a plurality of repeated pattern areas from layout information contained in the designed pattern data, reads the arrangement, the number, the dimension and the repeated pitch of the repeated pattern areas, and automatically fetches an inspection area of the die-to-die comparison method.
    Type: Application
    Filed: February 29, 2008
    Publication date: July 10, 2008
    Inventors: Hideo Tsuchiya, Kyoji Yamashita, Toshiyuki Watanabe, Ikunao Isomura, Toru Tojo, Yasushi Sanada
  • Publication number: 20080142898
    Abstract: An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
    Type: Application
    Filed: November 7, 2007
    Publication date: June 19, 2008
    Inventors: Shinji Watanabe, Daisaku Ikoma, Kyoji Yamashita, Katsuhiro Ootani