Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages V1 and V2, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A defect inspection apparatus includes a sensor which optically senses a circuit pattern formed on a plate to be inspected to obtain scanned image data thereof while moving relatively to the plate, an AD converter which converts the scanned image data into digital form, a normal image data generator which generates normal image data expressed by use of multiple values based on CAD data relating to the circuit pattern, a reference data generator which filters the normal image data to generate reference data while selecting filter coefficients according to the moving direction of the plate to be inspected by use of a finite response filter having asymmetrical coefficients, and a comparator which compares the reference data with the scanned image data.

Abstract: In a production line for obtaining a final product by performing a plurality of process steps on each of a plurality of products, when one of the process steps is finished, measured data is obtained by measuring the characteristics of a product on which the process step has been performed. Based on the measured data obtained, the performance of a final product is expected. And based on the expected performance of the final product, the number of products estimatingly finished for each performance rank thereof is calculated.

Abstract: It is an object to obtain a semiconductor device having a circuit for CBCM (Charge Based Capacitance Measurement) which can measure a capacitance value with high precision. An MOS transistor constituting a circuit for CBCM has the following structure. More specifically, source-drain regions (4) and (4′) are selectively formed in a surface of a body region (16), and extension regions (5) and (5′) are extended from tip portions of the source-drain regions (4) and (4′) opposed to each other, respectively. A gate insulating film 7 is formed between the source-drain regions (4) and (4′) including the extension regions (5) and (5′) and a gate electrode (8) is formed on the gate insulating film (7). A region corresponding to a pocket region 6 (6′) in a conventional structure having a higher impurity concentration than that of a channel region is not formed in a tip portion of the extension region 5 (5′) and a peripheral portion of the extension region (5).

Abstract: A pattern inspection apparatus determines a difference of the measured dislocation of respective alignment marks of an opaque pattern and a phase shifting pattern (measurement difference), in addition to a difference between the both alignment mark positions in design (design difference). A difference between the measurement difference and the design difference is set as a difference in alignment mark position between the opaque pattern and the phase shifting pattern in a reference pattern which is later used in inspection. In this manner, by correcting one pattern data with respect to the other pattern data in the reference pattern, the displacement generated in the both patterns can be reflected, and the reference pattern data regarding an image of a sample which is actually observed can be created.

Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.

Abstract: A defect inspection method for detecting defects of a pattern formed on a sample. The method has a step of inputting an optical image of the sample as a sensor data, a step of inputting a reference data corresponding to the sensor data, a step of inputting an inspection region data designating a plurality of inspection regions with a rectangular region R including one opening section as the inspection region, a step of extracting the sensor data and the reference data corresponding thereto from a respective one of the inspection regions as designated by the inspection region data and then calculating based thereon a transmission error and relative displacement, and a step of using the resultant transmission error and relative displacement to analyze transmission defects and critical dimension (CD) defects as well as relative displacement defects.

Abstract: A defect inspection apparatus capable of precluding, or at least minimizing, the risk of erroneous recognition while simulating an accurate optical image from design data, and using it as reference data in masks using based resolution enhancement techniques such as phase-shift masks, or else by performing defect inspection by optically reading a pattern on a test substrate having the pattern, converting it into scanned image data for use as electrical image information, and then comparing the scanned image data with reference data indicative of an optical image obtainable from design data of the test substrate by simulation.

Abstract: A defect inspection method for detecting defects of a pattern formed on a sample. The method has a step of inputting an optical image of the sample as a sensor data, a step of inputting a reference data corresponding to the sensor data, a step of inputting an inspection region data designating a plurality of inspection regions with a rectangular region R including one opening section as the inspection region, a step of extracting the sensor data and the reference data corresponding thereto from a respective one of the inspection regions as designated by the inspection region data and then calculating based thereon a transmission error and relative displacement, and a step of using the resultant transmission error and relative displacement, displacement to analyze transmission defects and critical dimension (CD) defects as well as relative displacement defects.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A method of designing an LSI circuit pattern which connects a plurality of gates on an LSI chip. The method estimates a chip area of the LSI chip and a number of the plurality of gates required for achieving a desired function; estimates an interconnect length of each of the plurality of gates; designs a wiring pattern associated with the each of the plurality of gates based on a prescribed design rule, and calculates a gate delay time for the design wiring pattern; alters the design rule as necessary if the calculated gate delay time exceeds a prescribed target value, while calculating the total area occupied by the designed wiring patterns when the calculated gate delay time is within a prescribed target value. The process sequentially repeats for a gate having a next shortest interconnect length when the calculated total area occupied by the designed wiring patterns does not exceed the estimated chip area.

Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.

Abstract: A single light emitted from a laser source is split into multiple beams. The multiple beams are illuminated by a multi-beam scanner to scan a substrate of interest. An optical system is provided for focusing the multiple beams independently on the substrate and directing a reflected light or a transmitted light of the multiple beams on the substrate. Aperture regulating members are disposed at equal intervals corresponding to the interval between the multiple beams for controlling the multiple beams directed from the substrate by the optical system. The multiple beams passed through their respective aperture regulating members are received by an optical detector assembly which detect a change in the amount of the multiple beams. The substrate is continuously moved by a movable table on a plane substantially vertical to the multiple beams and in a direction arranged at substantially a right angle to the scanning direction of the multiple beams.

Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.

Abstract: The semiconductor integrated circuit of this invention includes: a first converter for converting a plurality of input data signals into a composite serial data signal and outputting the composite serial data signal; a second converter for receiving the composite serial data signal via a data signal wiring and converting the composite serial data signal into a plurality of output data signals; and a clock signal supply section for supplying a clock signal for synchronizing an operation of the first converter and an operation of the second converter, wherein the clock signal is input into the first converter and the second converter via a clock signal wiring, the data signal wiring imparts a time delay to the composite serial data signal input into the second converter, and the clock signal wiring imparts a time delay to the clock signal input into the second converter.

Abstract: A method and an apparatus for generating, at a high speed, with high accuracy, a multi-gradation two-dimensional pattern without allowing graphic data of a two-dimensional circuit pattern to undergo bit development are provided. A scheme is employed to input coordinate values and external form dimensions of a plane figure to divide the coordinate values and the external form dimensions by sizes (dimensions) of pixels to normalize them to judge whether or not respective sides of the figure are included within the pixel sizes, whereby in the case where those sides are included, distances from central points of pixels to respective sides and angles thereof are determined with respect to all the pixels to determine density values of pixels by using the result to output the density values to an image memory to generate a two-dimensional circuit pattern within the memory.

Abstract: A MOS semiconductor device includes a first conductivity type silicon layer having a main surface; a gate insulating film selectively formed on the main surface of the silicon layer; a gate electrode provided on the gate insulating film; an insulating side wall formed on the side of the gate electrode; and source/drain regions formed in the silicon layer. The source/drain regions include a first diffusion layer of second conductivity type formed in the silicon layer; a second diffusion layer of second conductivity type formed in the silicon layer on the outside of the first diffusion layer and having a PN-junction depth larger than that of the first diffusion layer; and the MOS semiconductor device further includes a conductive layer covering at least part of the first diffusion layer and at least part of the second diffusion layer.