Patents by Inventor Kyoung Bong Rouh
Kyoung Bong Rouh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7824975Abstract: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.Type: GrantFiled: June 30, 2008Date of Patent: November 2, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yong Soo Joung, Kyoung Bong Rouh, Hye Jin Seo
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Patent number: 7825015Abstract: The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate and another method for fabricating a semiconductor device capable of improving distribution of transistor parameters inside a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile.Type: GrantFiled: December 30, 2004Date of Patent: November 2, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Yong-Sun Sohn, Seung-Woo Jin, Min-Yong Lee, Kyoung-Bong Rouh
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Patent number: 7790551Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.Type: GrantFiled: October 22, 2009Date of Patent: September 7, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7785945Abstract: A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the asymmetrically etched polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which delimits a region to be formed with a gate of the PMOS transistor, over the gate metal layer; forming a gate stack by patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer; and forming a source/drain in the semiconductor substrate at both sides of the gate stack.Type: GrantFiled: June 25, 2009Date of Patent: August 31, 2010Assignee: Hynix Semiconductor Inc.Inventor: Kyoung Bong Rouh
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Publication number: 20100167483Abstract: A method for fabricating a PMOS transistor is disclosed herein. In one embodiment, the method can include forming a gate insulation layer and a polysilicon layer over a semiconductor substrate; asymmetrically etching the polysilicon layer; doping the asymmetrically etched polysilicon layer with a P-type dopant; diffusing the dopant in the asymmetrically etched polysilicon layer towards the semiconductor substrate; planarizing the asymmetrically etched polysilicon layer; forming a gate metal layer over the planarized polysilicon layer; forming a hard mask, which delimits a region to be formed with a gate of the PMOS transistor, over the gate metal layer; forming a gate stack by patterning the gate metal layer, the planarized polysilicon layer, and the gate insulation layer; and forming a source/drain in the semiconductor substrate at both sides of the gate stack.Type: ApplicationFiled: June 25, 2009Publication date: July 1, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kyoung Bong Rouh
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Publication number: 20100117131Abstract: A transistor for preventing or reducing short channel effect includes a substrate; a gate stack disposed over the substrate; a first junction region disposed on the substrate at a first side surface of the gate stack, said first junction layer being formed of an epitaxial layer; a trench formed within the substrate at a second side surface of the gate stack; and a second junction region disposed below the trench, said second junction layer being lower than the first junction region.Type: ApplicationFiled: December 29, 2008Publication date: May 13, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Young Hwan Joo
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Publication number: 20100120240Abstract: Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.Type: ApplicationFiled: December 30, 2008Publication date: May 13, 2010Applicant: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Choon Hwan Kim, Il Cheol Rho
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Publication number: 20100099244Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.Type: ApplicationFiled: December 23, 2009Publication date: April 22, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Yong Sun Sohn, Min Yong Lee
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Patent number: 7700442Abstract: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.Type: GrantFiled: December 21, 2007Date of Patent: April 20, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee
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Patent number: 7687852Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: GrantFiled: February 16, 2009Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7687350Abstract: A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, forming a gate spacer layer at both sides of the gate stack, and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other.Type: GrantFiled: June 9, 2006Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventors: Min Yong Lee, Kyoung Bong Rouh, Seung Woo Jin
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Patent number: 7678653Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: GrantFiled: February 16, 2009Date of Patent: March 16, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Publication number: 20100041196Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.Type: ApplicationFiled: October 22, 2009Publication date: February 18, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7662705Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.Type: GrantFiled: August 4, 2005Date of Patent: February 16, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Yong Sun Sohn, Min Yong Lee
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Publication number: 20090267002Abstract: A partial ion implantation apparatus and method are provided. The partial ion implantation apparatus includes an ion beam generator, a wafer chuck, and a plurality of atom-vibrating devices. The ion beam generator is configured to generate an ion beam. The wafer chuck is disposed to support a wafer into which the ion beam is implanted. The atom-vibrating devices are configured to vibrate silicon atoms in the wafer.Type: ApplicationFiled: August 4, 2008Publication date: October 29, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Kyoung Bong Rouh
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Patent number: 7576339Abstract: An ion implantation apparatus includes an ion beam source for generating an ion beam; an implantation energy controller disposed on a path of the ion beam for controlling the ion implantation energy of the ion beam so that an ion beam having a first implantation energy is created for a first period of time and an ion beam having a second implantation energy is created for a second period of time; a beam line for accelerating the ion beam; and an end station for mounting a substrate, into which the ion beam accelerated by the beam line is implanted onto the substrate.Type: GrantFiled: June 2, 2006Date of Patent: August 18, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Jung, Yong Soo Jung
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Publication number: 20090173996Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: ApplicationFiled: February 16, 2009Publication date: July 9, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Publication number: 20090170297Abstract: A method of fabricating a semiconductor device having a gate spacer layer with a uniform thickness wherein a gate electrode layer pattern is formed on a substrate and ion implantation processes of respectively different doses are formed on side walls of the gate electrode layer patterns in respective first and second regions of the substrate. A first gate spacer layer is formed on the gate electrode layer pattern where the ion implantation process is performed. A second gate spacer layer is formed on the first gate spacer layer.Type: ApplicationFiled: June 30, 2008Publication date: July 2, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yong Soo Joung, Kyoung Bong Rouh, Hye Jin Seo
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Publication number: 20090170265Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: ApplicationFiled: February 16, 2009Publication date: July 2, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7554106Abstract: An ion implantation apparatus comprises an ion beam source for generating an initial ion beam, a bundled ion beam generator adapted to change the initial ion beam into a bundled ion beam based on a predetermined frequency to pass the bundled ion beam for a first time while passing the initial ion beam for a second time, a beam line for accelerating the ion beam having passed through the ion beam generator, and an end station for arranging a wafer therein to allow the ion beam accelerated by the beam line to be implanted in the wafer, the end station operating to move the wafer in a direction perpendicular to an ion beam implantation direction, so as to implant the bundled ion beam in a first region of the wafer and the initial ion beam in a second region of the wafer.Type: GrantFiled: June 1, 2006Date of Patent: June 30, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung