Abstract: Provided are an image sensor and a method of driving the same. The image sensor includes n optical black pixels which are arranged in the same horizontal line; and m comparators which are matched with the n optical black pixels, wherein n is a natural number greater than or equal to two, and m is a natural number greater than n.

Abstract: An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using a column selection signal. The pixel array includes a first pixel which is connected to the first row selection line and the first column line and a second pixel which is disposed in the same row as the first pixel and connected to the second row selection line and the second column line.

Abstract: An analog-to-digital converter includes a comparator, a switch, and a counter circuit. The comparator is configured to generate a comparison signal by comparing an analog signal received through a first signal line and a reference signal received through a second signal line. The switch is coupled between the first signal line and the comparator. The switch is open before the analog signal is applied to the first signal line to disconnect the first signal line from the comparator, and is closed after the analog signal is applied to the first signal line to provide the analog signal to the comparator. The counter circuit is configured to generate a digital signal corresponding to the analog signal by performing a count operation in synchronization with a count clock signal based on the comparison signal.

Abstract: An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using a column selection signal. The pixel array includes a first pixel which is connected to the first row selection line and the first column line and a second pixel which is disposed in the same row as the first pixel and connected to the second row selection line and the second column line.

Abstract: An image sensor can include a pixel array including a plurality of unit pixels and a row driver arranged in a matrix form that includes a plurality of rows and a plurality of columns. Respective ones of the unit pixels may convent an incident light to an electric signal and may store the electric signal. The row driver may sequentially scan the plurality of rows and may sequentially perform an electronic shutter operation and read-out operation. The electronic shutter operation may reset the stored electric signal in each unit pixel and the read-out operation may read-out the stored electric signal in each unit pixel. The electric shutter operation can include a preliminary shutter operation and a main shutter operation which are sequentially performed on one row. The row driver may overlap the main shutter operation on a first row and the preliminary shutter operation on a second row.

Abstract: An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.

Abstract: A correlated double sampling (CDS) circuit may include a sampling circuit and a switching circuit. The CDS circuit may perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal, and the CDS circuit may generate an output signal. The switching circuit may include an auto-zero switch that connects a first input terminal receiving the input signal to an output node in response to an auto-zero control signal during an auto-zero interval. The switching circuit may connect a first terminal of the auto-zero switch to a reference voltage in order to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval. The output signal may be provided at the output node.

Abstract: An image sensor is disclosed. The image sensor includes a plurality of pixels, a switch circuit coupled to the pixels and configured to substantially simultaneously output signals output only from pixels having similar characteristics among the pixels in response to a control signal; and a comparison circuit configured to convert the signals output from the switch circuit into digital signals. The pixels having similar characteristics are located across among the plurality of pixels.

Abstract: An image sensor is provided. The image sensor includes a pixel configured to generate a reset signal and an image signal, a comparator configured to compare the reset signal with a reference signal and generate a first comparison signal, a counter configured to generate a first count value corresponding to the reset signal based on a clock signal and the first comparison signal, and a reference signal generator configured to generate the reference signal which changes between a first level corresponding to a maximum reset count value of the counter and a second level corresponding to a minimum reset count value of the counter during a reset signal period.

Abstract: The image sensor includes a plurality of column lines, a plurality of active road circuits and a selection circuit. The plurality of column lines are each connected to a corresponding one of a plurality of pixels. The plurality of active road circuits are each connected to a corresponding one of the plurality of column lines. The selection circuit is configured to enable a portion of the plurality of active road circuits based on a plurality of column selection signals.

Abstract: A correlated double sampling (CDS) circuit may include a sampling circuit and a switching circuit. The CDS circuit may perform a CDS operation on a reset component of an input signal and an image component of the input signal based on a ramp signal, and the CDS circuit may generate an output signal. The switching circuit may include an auto-zero switch that connects a first input terminal receiving the input signal to an output node in response to an auto-zero control signal during an auto-zero interval. The switching circuit may connect a first terminal of the auto-zero switch to a reference voltage in order to cutoff a leakage current flowing to the auto-zero switch in response to a first boosting control signal during a first comparison interval and a second comparison interval. The output signal may be provided at the output node.

Abstract: An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n?1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n?1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.

Abstract: An image sensor includes a pixel array in which a plurality of pixels, first and second row selection lines separated from each other, and first and second column lines separated from each other are disposed and a column selecting circuit configured to connect the first and second column lines using a column selection signal. The pixel array includes a first pixel which is connected to the first row selection line and the first column line and a second pixel which is disposed in the same row as the first pixel and connected to the second row selection line and the second column line.

Abstract: A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

Abstract: A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

Abstract: An image sensor includes a pixel array including a plurality of pixels, a row driver configured to control an operation of each of the plurality of pixels, a voltage supply line connected to a reset transistor included in each of the plurality of pixels, and a voltage supply circuit which detects a signal from the voltage supply line and supplies one of a first voltage and a second voltage to the voltage supply line based on the signal from the voltage supply line.

Abstract: Provided are an image sensor and a method of driving the same. The image sensor includes n optical black pixels which are arranged in the same horizontal line; and m comparators which are matched with the n optical black pixels, wherein n is a natural number greater than or equal to two, and m is a natural number greater than n.

Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.

Abstract: An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.