Abstract: The image sensor includes a plurality of column lines, a plurality of active road circuits and a selection circuit. The plurality of column lines are each connected to a corresponding one of a plurality of pixels. The plurality of active road circuits are each connected to a corresponding one of the plurality of column lines. The selection circuit is configured to enable a portion of the plurality of active road circuits based on a plurality of column selection signals.

Abstract: An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio.

Abstract: A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.

Abstract: An image sensor includes a first column pair and a second column pair among a plurality of columns of a pixel array, an analog-to-digital converter pair, and a switch arrangement circuit configured to connect the first column pair with the analog-to-digital converter pair in response to first switch control signals such that two rows among a plurality of rows in the pixel array are read during a single access time.

Abstract: An example embodiment of an image sensor may include a controller and a plurality of up/down ripple counters. The controller may generate a first control signal and a second control signal. Each of the up/down ripple counters may perform a stop operation or a count operation in response to a corresponding one of a plurality of operation control signals generated based on at least in part on the first control signal. The count operation may be an up-count operation or a down-count operation based on the second control signal. The image sensor may also include a plurality of memory chains. Each of the memory chains may receive a count value output from the up/down counters and may shift the received count value in response to a third control signal and a fourth control signal output from the controller.

Abstract: The image sensor includes a plurality of column lines, a plurality of active road circuits and a selection circuit. The plurality of column lines are each connected to a corresponding one of a plurality of pixels. The plurality of active road circuits are each connected to a corresponding one of the plurality of column lines. The selection circuit is configured to enable a portion of the plurality of active road circuits based on a plurality of column selection signals.

Abstract: An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n-1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n-1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.

Abstract: An example embodiment of an image sensor may include a controller and a plurality of up/down ripple counters. The controller may generate a first control signal and a second control signal. Each of the up/down ripple counters may perform a stop operation or a count operation in response to a corresponding one of a plurality of operation control signals generated based on at least in part on the first control signal. The count operation may be an up-count operation or a down-count operation based on the second control signal. The image sensor may also include a plurality of memory chains. Each of the memory chains may receive a count value output from the up/down counters and may shift the received count value in response to a third control signal and a fourth control signal output from the controller.

Abstract: A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.

Abstract: An image sensor includes a reference voltage generation unit that generates a reference voltage that alternately decreases and increases at a constant rate in an operation mode of the image sensor to convert analog signals of detected incident light to a digital value using the reference voltage to determine an intensity of the incident light with high sensitivity and high signal-to-noise ratio.

Abstract: An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

Abstract: An example embodiment of an image sensor may include a controller and a plurality of up/down ripple counters. The controller may generate a first control signal and a second control signal. Each of the up/down ripple counters may perform a stop operation or a count operation in response to a corresponding one of a plurality of operation control signals generated based on at least in part on the first control signal. The count operation may be an up-count operation or a down-count operation based on the second control signal. The image sensor may also include a plurality of memory chains. Each of the memory chains may receive a count value output from the up/down counters and may shift the received count value in response to a third control signal and a fourth control signal output from the controller.

Abstract: A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.

Abstract: A counter array and an image sensor including the same may be provided. The counter array may include a controller and a plurality of counter units. The controller may output an operation control signal and a direction indication signal. The counter units hold previous output values or may perform a counting operation in response to the operation control signal and may perform an up-count operation or a down-count operation in response to the direction indication signal when performing the counting operation.

Abstract: In one embodiment, the boost circuit includes a boost unit configured to perform a charge pumping operation based on a control signal. A controller is configured to control the boost unit such that the boost unit performs a lesser charge pumping operation from an initial time when power is supplied to the boost circuit until a desired time than after the desired time.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.

Abstract: A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.

Abstract: The image sensor includes a plurality of column lines, a plurality of active road circuits and a selection circuit. The plurality of column lines are each connected to a corresponding one of a plurality of pixels. The plurality of active road circuits are each connected to a corresponding one of the plurality of column lines. The selection circuit is configured to enable a portion of the plurality of active road circuits based on a plurality of column selection signals.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.