Patents by Inventor Kyoung-Min Lee

Kyoung-Min Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12237836
    Abstract: In some examples, a circuit includes a capacitor having a first terminal and a second terminal, the first terminal coupled to a voltage supply terminal of the circuit. The circuit also includes a transistor having a transistor gate, a transistor drain, and a transistor source, the transistor source coupled to ground and the transistor drain coupled to an input terminal of the circuit. The transistor is configured to conduct responsive to a gate signal received at the transistor gate, the gate signal based on a signal provided at the second terminal of the capacitor. The circuit also includes a Schmitt trigger having a Schmitt trigger input coupled to the transistor drain.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 25, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kyoung Min Lee, Satish Kumar Vemuri, Zhidong Liu, Maxim James Franke, Kory Andrew McCarthy
  • Publication number: 20250062766
    Abstract: A driver includes a current generator having an input and first and second outputs. The current generator generates a first current at the first output while a signal at the input is at a first logic state and generates a second current at the second output while the signal at the input is at a second logic state. A comparator has a first comparator input, a second comparator input, and a first comparator output, and a second comparator output. The first comparator input is coupled to the first output, and the second comparator input is coupled to the second output. A latch has a first latch input, a second latch input, and a latch output. The first latch input is coupled to the first comparator output, and the second latch input is coupled to the second comparator output. A gate control circuit has an input coupled to the latch output.
    Type: Application
    Filed: October 20, 2023
    Publication date: February 20, 2025
    Inventors: Kyoung Min Lee, Satish Vemuri
  • Publication number: 20240404929
    Abstract: An electronic device includes a leadframe having a die pad and leads. A die having an active side is attached to the die pad. The die further includes a dielectric layer deposited on a side of the die opposite that of the active side and an die attach film deposited on the dielectric layer. Wire bonds are attached from the active side of the die to the leads. A critical signal wire bond is attached from the active side of the die to the die pad. A mold compound encapsulates the die, the wire bonds, the critical signal wire bond, and a portion of the leadframe. A stacked formation of the die, the dielectric layer, and the die attach film form a capacitor that filters noise from a critical signal carried by the critical signal wire bond.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Kapil Sahasrabudhe, Kyoung Min Lee, Philomena Brady
  • Publication number: 20240405017
    Abstract: A microelectronic device including an integrated boot diode and a depleted mode LDMOS transistor with a charge balance layer isolated from the body region and electrically in contact with a substrate. The connection of the charge balance layer of the depleted mode LDMOS transistor directly to the substrate or ground reference eliminates body diode turn-on from the body of the transistor to the drain which typically happens above approximately 0.7 volts. In addition, the depleted mode LDMOS transistor may separate a source contact from a body contact which allows a negative bias of the body with respect to the source. Typically, the source voltage is limited to approximately 7 volts before parasitic PNP turn on becomes a factor. By negatively biasing the body with respect to the source, the maximum source voltage of the depleted mode LDMOS transistor without PNP parasitic turn-on may be increased to approximately 30 V.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Dong Seup Lee, Sunglyong Kim, Kyoung Min Lee
  • Publication number: 20240371718
    Abstract: A semiconductor package includes a first package substrate including a first redistribution layer, at least one semiconductor chip disposed on the first redistribution layer and including a semiconductor device, and a second package substrate disposed on the at least one semiconductor chip and including a second redistribution layer. The at least one semiconductor chip includes at least one heat dissipation via having one end adjacent to the semiconductor device and penetrating through at least a portion of the at least one semiconductor chip, and another end contacting the second package substrate. The at least one heat dissipation via is a dissipation path of heat generated from the semiconductor device.
    Type: Application
    Filed: November 13, 2023
    Publication date: November 7, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Daehan YOUN, Youngsang CHO, Kyoung-Min LEE, Junho HUH
  • Publication number: 20240282672
    Abstract: A semiconductor device includes: a package substrate; a first die on the package substrate and including a hard macro and through silicon vias; and a second die on the first die, wherein the first die includes a first region, which does not include the hard macro, and a second region including a macro-region that includes the hard macro, wherein the through silicon vias of the first region are arranged in a first direction with a first distance and in a second direction with a second distance, wherein the through silicon vias of the second region are arranged in the first direction with a first pitch, and in the second direction with a second pitch, wherein the macro-region is interposed between the through silicon vias arranged in the first direction, wherein the first pitch is greater than the first distance, and wherein the second pitch is less than the second distance.
    Type: Application
    Filed: November 14, 2023
    Publication date: August 22, 2024
    Inventors: BONGWEE YU, KYOUNG -MIN LEE, KYUNGSOO LEE, JUNHO HUH
  • Patent number: 12028066
    Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: July 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kyoung Min Lee, James M. Walden, Brian Linehan, Yang Zhang
  • Publication number: 20230392174
    Abstract: The present invention relates to a microorganism for producing putrescine and a method for producing putrescine by using same.
    Type: Application
    Filed: March 19, 2021
    Publication date: December 7, 2023
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Jaehun Lee, Kyoung Min Lee, Hyun-jung Bae
  • Publication number: 20230357501
    Abstract: A polyethylene glycol derivative compound is represented by Formula 1 described in the detailed description. In Formula 1, n is a natural number of 30 to 115, and R1 and R2 are C1 to C5 alkyl that are identical to or different from each other.
    Type: Application
    Filed: September 16, 2021
    Publication date: November 9, 2023
    Applicants: HANMI FINE CHEMICAL CO., LTD., HANMI PHARM. CO., LTD.
    Inventors: Ji Hye MOON, Yeon Jeong JANG, Hyun Jung SHIM, Eun Hye KIM, Tae In EOM, Su Mi LEE, Yu Rim KIM, Yong Gyu JUNG, Ji Hye KIM, Soon Ah AHN, Wok Chul YOO, Young Bum CHO, Kyoung Min LEE, Jae Heon LEE
  • Patent number: 11782466
    Abstract: To dynamically manage a temperature of an electronic device, a local temperature is provided by measuring a temperature of a local spot in the electronic device and a reference temperature is provided by measuring a temperature of a reference spot in the electronic device where the reference spot and the local spot are thermally coupled. A target temperature corresponding to a limit value of the reference temperature is adjusted based on the local temperature and a power level of the electronic device is controlled based on the same target temperature. The target temperature may be set to a relatively high value to secure performance of the electronic device when the local temperature is relatively low. Alternatively, the target temperature may be set to a relatively low value to pursue stability of the electronic device when the local temperature is relatively high.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 10, 2023
    Inventors: Yun-Hyeok Im, Myung-Kyoon Yim, Wook Kim, Kyoung-Min Lee, Kyung-Soo Lee
  • Publication number: 20230318588
    Abstract: In some examples, a circuit includes a capacitor having a first terminal and a second terminal, the first terminal coupled to a voltage supply terminal of the circuit. The circuit also includes a transistor having a transistor gate, a transistor drain, and a transistor source, the transistor source coupled to ground and the transistor drain coupled to an input terminal of the circuit. The transistor is configured to conduct responsive to a gate signal received at the transistor gate, the gate signal based on a signal provided at the second terminal of the capacitor. The circuit also includes a Schmitt trigger having a Schmitt trigger input coupled to the transistor drain.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Kyoung Min LEE, Satish Kumar VEMURI, Zhidong LIU, Maxim James FRANKE, Kory Andrew McCARTHY
  • Publication number: 20230282624
    Abstract: An integrated circuit chip includes; a package substrate including a first signal ball, a first semiconductor chip on the package substrate, a second semiconductor chip on the first semiconductor chip, a first bump disposed between the package substrate and the first semiconductor chip and electrically connected to the first signal ball, and a second bump disposed between the first semiconductor chip and the second semiconductor chip and electrically connected to the first signal ball, wherein during a first mode, the first signal ball receives a signal from the first semiconductor chip through the first bump and receives a signal from the second semiconductor chip through the second bump.
    Type: Application
    Filed: November 25, 2022
    Publication date: September 7, 2023
    Inventors: BONG WEE YU, EUN-HEE KIM, KYOUNG-MIN LEE
  • Patent number: 11744461
    Abstract: The present disclosure relates to a retina imaging method in which a light from a light source into two lights is dispersed, at least one eyeground image of the eyeball at a first magnification is obtained by adjusting the paths of the two lights incident on the eyeball, and a plurality of DIC images are obtained at a second magnification higher than the first magnification with respect to the retina of the entirety of the obtained at least one eyeground image by adjusting the paths of the two lights incident on the eyeball.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 5, 2023
    Assignees: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY, SEOUL NATIONAL UNIVERSITY HOSPITAL, INHA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Jae Hun Kim, Dae Yu Kim, Seok Hwan Kim, Youngho Cho, Byeongho Park, Hyo-suk Kim, Subeen Park, Kyoung Min Lee
  • Publication number: 20230261657
    Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.
    Type: Application
    Filed: April 27, 2023
    Publication date: August 17, 2023
    Inventors: Kyoung Min Lee, James M. Walden, Brian Linehan, Yang Zhang
  • Patent number: 11671098
    Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: June 6, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kyoung Min Lee, James M. Walden, Brian Linehan, Yang Zhang
  • Patent number: 11492648
    Abstract: The present disclosure relates to a novel polypeptide having an ability to export an ornithine-based product, and a method for producing an ornithine-based product using the same.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: November 8, 2022
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Seon Hye Kim, Su Jin Park, Kyoung Min Lee, Kyungsu Na, Hong Xian Li, Hyun-jung Bae, Jihyun Shim, Young Lyeol Yang, Hye Won Um, Hyo Hyoung Lee, Min Gyeong Kang, Hye Won Kim, Byeong Cheol Song, Haena Oh, Han Hyoung Lee
  • Patent number: 11444617
    Abstract: A set and reset pulse generator circuit receives an input signal to generate a set signal and a reset signal pair. The set and reset pulse generator circuit includes a set circuit and a reset circuit. A cross-coupling circuit connects a voltage signal of the reset circuit to an output circuit of the set circuit, and another cross-coupling circuit connects a voltage signal of the set circuit to an output circuit of the reset circuit. The output circuit of the set circuit generates the set signal from the input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit. The output circuit of the reset circuit generates the reset signal from an inverted input signal, the voltage signal of the reset circuit, and the voltage signal of the set circuit.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: September 13, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kyoung Min Lee, Kaitlyn Sitch
  • Patent number: 11423674
    Abstract: A computer includes a processor and a memory, the memory storing instructions executable by the processor to determine respective probabilities of a direction of a gaze of a vehicle occupant toward each of a plurality of points in an image, determine a gaze distance from a center of the image based on the probabilities, and, upon determining that the gaze distance exceeds a threshold, suppress manual control of at least one vehicle component.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 23, 2022
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Kyoung Min Lee, Parthasarathy Subburaj, Durga Priya Kumar, Tilak D
  • Publication number: 20220216872
    Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Inventors: Kyoung Min Lee, James M. Walden, Brian Linehan, Yang Zhang
  • Patent number: 11365400
    Abstract: Disclosed is a modified microorganism producing putrescine or ornithine, and a method for producing putrescine or ornithine using the same.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: June 21, 2022
    Assignee: CJ Cheiljedang Corporation
    Inventors: Su Jin Park, Young Lyeol Yang, Hye Won Um, Hong Xian Li, Kyoung Min Lee, Baek Seok Lee, Hyo Hyoung Lee, Hee Kyoung Jung