Abstract: The present invention relates to an organic electroluminescent device comprising at least one light-emitting layer between an anode and a cathode, wherein the light-emitting layer comprises a host and a phosphorescent dopant; the host comprises plural host compounds; at least a first host compound of the plural host compounds has a structure of a nitrogen-containing heterocyclic linker bonded to a nitrogen atom of a carbazole of an indole-carbazole, indene-carbazole, benzofuran-carbazole, or benzothiophene-carbazole residue; and a second host compound has a carbazole-aryl-carbazole or carbazole-carbazole structure. According to the present invention, by using a specific multi-component host different from the conventional organic electroluminescent device, an organic electroluminescent device of significantly improved lifespan is provided.

Abstract: Disclosed is an image sensing system including an image sensor suitable for generating first actual brightness values corresponding to a captured image; and an image processor suitable for compensating for the first actual brightness values for each brightness period in a single frame period based on compensation information corresponding to a linearity error.

Abstract: Disclosed is an image sensing device including a plurality of defect detectors each suitable for detecting whether a corresponding target image value is defective, and generating detection information corresponding to a result of the detection, a defect scheduler suitable for sequentially outputting one or more defective image values, which are the target image values detected as defective among the plurality of target image values, based on the detection information, and a defect corrector suitable for correcting the output defective image values.

Abstract: Disclosed is an image sensor including a first sub-pixel array including a plurality of first pixel groups, which are respectively coupled to a plurality of first readout lines extending in a first direction and are adjacent to one another in a second direction intersecting the first direction; and a plurality of first switches suitable for selectively coupling a plurality of first floating diffusion nodes included in the plurality of first pixel groups, based on a plurality of first control signals.

Abstract: Disclosed is an image sensing device including a plurality of defect detectors each suitable for detecting whether a corresponding target image value is defective, and generating detection information corresponding to a result of the detection, a defect scheduler suitable for sequentially outputting one or more defective image values, which are the target image values detected as defective among the plurality of target image values, based on the detection information, and a defect corrector suitable for correcting the output defective image values.

Abstract: Disclosed is an image sensing system including an image sensor suitable for generating first actual brightness values corresponding to a captured image; and an image processor suitable for compensating for the first actual brightness values for each brightness period in a single frame period based on compensation information corresponding to a linearity error.

Abstract: A display driving circuit includes a timing controller including an encoder that compresses image data based on a reference having a number of image pixels of the image data as a compression unit and that outputs the compressed image data. The timing controller further includes at least one source driver including a decoder that decompresses compressed image data and transmits decompressed image data to a display panel through a plurality of channels. Compression by the encoder based on a first reference is performed independently of compression based on a second reference.

Abstract: A display driving circuit includes a timing controller including an encoder that compresses image data based on a reference having a number of image pixels of the image data as a compression unit and that outputs the compressed image data. The timing controller further includes at least one source driver including a decoder that decompresses compressed image data and transmits decompressed image data to a display panel through a plurality of channels. Compression by the encoder based on a first reference is performed independently of compression based on a second reference.

Abstract: A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.

Abstract: A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.

Abstract: A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from the system-on-chip through the SOC bump groups. The SOC bump groups are arranged and the at least one wide input/output memory device is configured such that one of the wide input/output memory devices can be mounted to the SOC as connected to all of the SOC bump groups, or such that two wide input/output memory devices can be mounted to the SOC with each of the wide input/out memory devices connected a respective half of the SOC bump groups.

Abstract: A deblocking filter includes a color resolution expansion unit, an edge filtering unit and a color resolution contraction unit. The color resolution expansion unit increases a color resolution of input video data to generate first video data. The edge filtering unit performs a blurring operation on a block edge of the first video data based on block size information to generate second video data. The color resolution contraction unit reduces a color resolution of the second video data to generate output video data, a color resolution of the output video data being the same as the color resolution of the input video data.

Abstract: A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from the system-on-chip through the SOC bump groups. The SOC bump groups are arranged and the at least one wide input/output memory device is configured such that one of the wide input/output memory devices can be mounted to the SOC as connected to all of the SOC bump groups, or such that two wide input/output memory devices can be mounted to the SOC with each of the wide input/out memory devices connected a respective half of the SOC bump groups.

Abstract: A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets.

Abstract: An image processing device is provided. The image processing device includes a weighted low-pass filter which performs weighted low-pass filtering on illumination of sub-sampled pixel signals, and an illumination interpolation circuit which compares illumination of the weighted low-pass filtered pixel signals with illumination of current pixel signals and performs interpolation while applying a weight to illumination of the weighted low-pass filtered pixel signals according to the comparison result.

Abstract: A multi-core processor includes first processor core including a first instruction fetch unit and out-of-order execution data units, a second processor core including a second instruction fetch unit and in-order execution data units, and a shared-level 1 cache including a level 1-instruction cache shared between the first instruction fetch unit and the second instruction fetch unit and a level 1-data cache shared between the out-of-order execution data units and the in-order execution data.

Abstract: An image processing device is provided. The image processing device includes a weighted low-pass filter which performs weighted low-pass filtering on illumination of sub-sampled pixel signals, and an illumination interpolation circuit which compares illumination of the weighted low-pass filtered pixel signals with illumination of current pixel signals and performs interpolation while applying a weight to illumination of the weighted low-pass filtered pixel signals according to the comparison result.

Abstract: A flash memory system includes a memory unit including a main cell that stores main data and a parity cell that stores parity data, and an ECC receiving a codeword including the stored main data and the stored parity data, performing error correction on the codeword by executing an operation on a finite field with respect to the codeword, and an element of the finite field comprising a codeword corresponding to an erased page of the memory unit.

Abstract: An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.

Abstract: A deblocking filter includes a color resolution expansion unit, an edge filtering unit and a color resolution contraction unit. The color resolution expansion unit increases a color resolution of input video data to generate first video data. The edge filtering unit performs a blurring operation on a block edge of the first video data based on block size information to generate second video data. The color resolution contraction unit reduces a color resolution of the second video data to generate output video data, a color resolution of the output video data being the same as the color resolution of the input video data.