Abstract: A digital video signal processing apparatus and method for field-based adaptive Y/C separation includes an adaptive 3D BPF performing Y/C separation according to local comb filtering/1D band pass filtering when the edge direction is fixed vertically/horizontally in response to spatio-temporal local characteristics of an image using spatio-temporal filters. When the edge direction is not fixed horizontally or vertically, the 3D BPF performs 2D/3D band pass filtering in all directions. The 3D BPF adaptively and continuously carries out comb filtering, 1D band pass filtering and 2D/3D band pass filtering in response to the spatio-temporal local characteristics of the image.

Abstract: A digital video signal processing apparatus and method for frame-based adaptive spatio-temporal Y/C separation. In the digital video signal processing apparatus, an adaptive three-dimensional bandpass filter (3D BPF) performs Y/C separation using local comb filtering/1D band pass filtering/frame comb filtering when the edge direction is fixed vertically/horizontally/temporally according to spatio-temporal local characteristics of an image using spatio-temporal filters. When the edge direction is not fixed horizontally/vertically/temporally, the 3D BPF performs 2D or 3D band pass filtering in all directions. Thus, the 3D BPF continuously carries out comb filtering, 1D band pass filtering, frame comb filtering and 2D/3D band pass filtering according to the spatio-temporal local characteristic of the image.

Abstract: A digital video signal processing apparatus and method for detecting data in a vertical blanking interval (VBI) includes a re-sampler generating, from input video data, first re-sample data at a VBI data rate and second re-sample data with a data rate twice as high as the VBI data rate, a signal tracking unit tracking an existence of a clock run-in and a phase of the clock run-in from the second re-sample data and calculating an average of the clock run-in, and a slicer determining a logical value of the first re-sample data according to the average of the clock run-in and outputting the determined logical value as VBI data, wherein the re-sampler determines a compensation phase from the tracked phase of the clock run-in, re-samples the input video data according to the compensation phase with the VBI data rate and generates the first re-sample data.

Abstract: Video signal processing systems and methods for detecting horizontal synchronization signals within video signals. Digital filtering methods are implemented for processing analog video signals to determine time varying characteristics of video signals to detect the starting and ending positions of horizontal synchronization pulses in a video signal with increased accuracy. In addition, adaptive methods are implemented for dynamically determining various video signal parameters over time, such as blanking level BL, threshold value (slice) level and synchronization level SL using information extracted from digitally filtered video signals.

Abstract: An adaptive digital video signal processing apparatus and method for Y/C separation. In the video signal processing apparatus, an adaptive 2D BPF carries out Y/C separation through comb filtering and bandpass filtering selected according to local characteristics of an image (e.g., based on the direction in which an edge in the image extends in vertical and horizontal directions. The adaptive 2D BPF performs 2D bandpass filtering in general case. The 2D BPF adaptively executes a series of selections of the various filtering operations in a continuous manner.

Abstract: A digital processing system and method for tracking a subcarrier included in a video signal are provided, where a phase comparator tracks the phase of a color burst signal based on predetermined supposed phases, Y/C separation and demodulation are carried out based on a compensation phase that is updated by a phase compensator in response to the tracked phase, and the Y/C separation and demodulation are performed based on a compensation frequency determined by a frequency compensator by checking short-term and long-term variations in the updated compensation phase.

Abstract: An image data processing system with a memory performing burst read/write operations. The memory includes a memory cell array provided with memory cells arranged in a plurality of rows and a plurality of columns. The image data processing system further includes a controller for controlling an operation of reading/writing the image data from/to the memory. The controller divides the image data into a plurality of segments when a horizontal size of the image data is larger than a column width of the memory. An (I+1)-th (where I is a positive integer) segment includes a last burst data of an I-th segment, or the I-th segment includes a first burst data of the (I+1)-th segment. The respective segments correspond to the plurality of rows of the memory.

Abstract: Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the largest number of pending requests priorities; and write request information generated by masters is stored in a predetermined buffer to be output as additional master request information, and provides the corresponding master with an opportunity to generate new request information.

Abstract: An apparatus and method of controlling a digital video (MPEG) player for reverse-play. The MPEG player is comprised of an I-frame buffer for storing I-pictures encoded from P-pictures by a video decoder, a B-frame buffer for storing B-pictures, and an I-frame encoder for decoding a P-picture into an I-picture. In the MPEG player, a picture group being played at present is decoded for reverse play and a previous picture group is decoded for preparation of the reverse-play. Reverse-play in soft 1-times (×1) by means of a frame memory of small capacity is achieved irrespective of the picture number and classes in picture groups.

Abstract: An arbiter, a system, and a method for generating a pseudo-grant signal in response to a request and receiving target information in response to the pseudo-grant signal. The pseudo-grant signal reduces or eliminates waiting time.

Abstract: An image data processing system with a memory performing burst read/write operations. The memory includes a memory cell array provided with memory cells arranged in a plurality of rows and a plurality of columns. The image data processing system further includes a controller for controlling an operation of reading/writing the image data from/to the memory. The controller divides the image data into a plurality of segments when a horizontal size of the image data is larger than a column width of the memory. An (I+1)-th (where I is a positive integer) segment includes a last burst data of an I-th segment, or the I-th segment includes a first burst data of the (I+1)-th segment. The respective segments correspond to the plurality of rows of the memory.

Abstract: Provided is a computer system embedding buffers therein for improving the performance of a digital signal processing (DSP) data access operation and a method thereof. The computer system comprises a DSP core, a data cache, first and second buffer modules, and an external memory. The computer system further comprises a central processing unit (CPU) core. The CPU core executes instructions to control operations in the system and the DSP core processes data in accordance with instructions provided from the CPU core. The data cache stores temporary data generated during operations in the DSP core. The first buffer module stores input data forwarded to the DSP core while the second buffer module stores' output data provided from the DSP core. The external memory stores the temporary data, the input data, and the output data.

Abstract: The disclosure is a data processing device with selective data cache architecture and a computer system including the data processing device. The data processing device is comprised of a microprocessor, a coprocessor, a microprocessor data cache, an X-data cache, and a Y-data cache. The microprocessor fetches and executes instructions, and the coprocessor carries out digital signal processing functions. The microprocessor data cache stores data provided from the microprocessor. The X-data cache stores a first group of data provided from the coprocessor while the Y-data cache stores a second group of data provided from the coprocessor.

Abstract: Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding unit configured to constitute a VLIW instruction to be currently executed among the VLIW instructions stored in the packet buffer and decode predetermined bits of each sub-instruction contained in the VLIW instruction. The apparatus dispatches a corresponding sub-instruction to an FU which corresponds to each sub-instruction, based on the results of decoding performed in the decoding unit, position information on the sub-instructions that are placed on the packet buffer, and position information on the sub-instructions that are placed in the current VLIW instruction. Sub-instructions can be effectively dispatched to corresponding FUs using simple decoding logic even in a case where the length of the VLIW instruction is not fixed.

Abstract: Disclosed is a novel n-bit binary counter with low power consumption, which comprises a set of half-adders for adding a “1” to an n-bit input signal, which includes a lower-order m bit component and a higher-order (n−m) bit component, and a set of D (data) flip-flops for storing outputs of the half-adders. The set of half-adders are divided into two sections, one of which is a first adder section for adding a “1” to the lower-order m bit component and the other of which is a second adder section for adding a carry signal from the first adder section to the higher-order (n−m) bit component. The set of D flip-flops are divided into two sections, one of which is a first register section to store outputs of the first adder section and the other of which is a second register section to store outputs of the second adder section. The n-bit input signal is comprised of the outputs of the first and second register sections.