Patents by Inventor Kyoung-moon Ahn
Kyoung-moon Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220318436Abstract: An integrated circuit including: a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value; a selector configured to output a first signal obtained by not inverting a cell signal output by a PUF cell selected from the plurality of PUF cells and a second signal obtained by inverting the cell signal; and a key generator configured to generate a security key in response to the first signal or the second signal, wherein the selector includes a first conversion circuit configured to generate the first signal and a second conversion circuit having the same structure as the first conversion circuit and configured to generate the second signal.Type: ApplicationFiled: June 23, 2022Publication date: October 6, 2022Inventors: Bohdan Karpinskyy, Yong-ki LEE, Ji-eun Park, Kyoung-moon Ahn, Yun-Hyeok Choi
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Patent number: 11403432Abstract: An integrated circuit including: a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value; a selector configured to output a first signal obtained by not inverting a cell signal output by a PUF cell selected from the plurality PUF cells and a second signal obtained by inverting the cell signal; and a key generator configured to generate a security key in response to the first signal or the second signal, wherein the selector includes a first conversion circuit configured to generate the first signal and a second conversion circuit having the same structure as the first conversion circuit and configured to generate the second signal.Type: GrantFiled: August 28, 2019Date of Patent: August 2, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bohdan Karpinskyy, Yong-ki Lee, Ji-eun Park, Kyoung-moon Ahn, Yun-hyeok Choi
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Publication number: 20200210628Abstract: An integrated circuit including: a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value; a selector configured to output a first signal obtained by not inverting a cell signal output by a PUF cell selected from the plurality PUF cells and a second signal obtained by inverting the cell signal; and a key generator configured to generate a security key in response to the first signal or the second signal, wherein the selector includes a first conversion circuit configured to generate the first signal and a second conversion circuit having the same structure as the first conversion circuit and configured to generate the second signal.Type: ApplicationFiled: August 28, 2019Publication date: July 2, 2020Inventors: BOHDAN KARPINSKYY, Yong-ki Lee, Ji-eun Park, Kyoung-moon Ahn, Yun-hyeok Choi
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Patent number: 10693625Abstract: An application processor includes a security processor. An operating method of the security processor includes generating a recoder input including a digit-unit multiplier and a reference bit. At least one random bits having a random value are generated. When the recoder input has a predetermined pattern, the recoder input is converted into a first recoding value or a second recoding value according to a random bit corresponding to the recoder input to generate a recoding result.Type: GrantFiled: April 12, 2017Date of Patent: June 23, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Su Kang, Kyoung-Moon Ahn, Yong-Ki Lee, Ki-Seok Bae
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Patent number: 10210350Abstract: An embodiment includes an electronic device, comprising: a control intellectual property (IP) including a plurality of first special function registers (SFRs); a basic operation IP including a plurality of second SFRs and coupled to the control IP through a first path and a second path; and a random number generator configured to generate a random signal; wherein the control IP is configured to: select one of the first path and the second path based on the random signal; and set the second SFRs using the selected path.Type: GrantFiled: July 25, 2016Date of Patent: February 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Moon Ahn, Jong-Hoon Shin, Ki-Seok Bae
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Publication number: 20180152288Abstract: An application processor includes a security processor. An operating method of the security processor includes generating a recoder input including a digit-unit multiplier and a reference bit. At least one random bits having a random value are generated. When the recoder input has a predetermined pattern, the recoder input is converted into a first recoding value or a second recoding value according to a random bit corresponding to the recoder input to generate a recoding result.Type: ApplicationFiled: April 12, 2017Publication date: May 31, 2018Inventors: JI-SU KANG, KYOUNG-MOON AHN, YONG-KI LEE, KI-SEOK BAE
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Publication number: 20170046537Abstract: An embodiment includes an electronic device, comprising: a control intellectual property (IP) including a plurality of first special function registers (SFRs); a basic operation IP including a plurality of second SFRs and coupled to the control IP through a first path and a second path; and a random number generator configured to generate a random signal; wherein the control IP is configured to: select one of the first path and the second path based on the random signal; and set the second SFRs using the selected path.Type: ApplicationFiled: July 25, 2016Publication date: February 16, 2017Inventors: Kyoung-Moon AHN, Jong-Hoon SHIN, Ki-Seok BAE
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Patent number: 9164732Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.Type: GrantFiled: December 23, 2013Date of Patent: October 20, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ki Lee, Sun-Soo Shin, Jonghoon Shin, Kyoung Moon Ahn, Ji-Su Kang, Kee Moon Chun
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Patent number: 9043377Abstract: A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.Type: GrantFiled: January 30, 2012Date of Patent: May 26, 2015Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Young Sik Kim, Kyoung Moon Ahn, Jong Hoon Shin, Sun-Soo Shin, Ji-Su Kang
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Publication number: 20140192977Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.Type: ApplicationFiled: December 23, 2013Publication date: July 10, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Yong Ki LEE, Sun-Soo SHIN, Jonghoon SHIN, Kyoung Moon AHN, Ji-Su KANG, Kee Moon CHUN
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Patent number: 8756268Abstract: A radix-2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the multiplicand, the modulus and the sum, and to divide and to output the received previous sum into units of k bits, an accumulator circuit to receive the partial product, the multiple modulus and k bits of the previous sum from the input coefficient generation unit, and to generate and to output a carry and a sum by summing the partial product, the multiple modulus and the previous sum, and a carry propagation adder (CPA) circuit to generate and to output an ultimate sum by using the carry and the sum.Type: GrantFiled: March 21, 2011Date of Patent: June 17, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Kyoung-moon Ahn, Young-sik Kim, Jong-hoon Shin, Sun-soo Shin, Ji-su Kang
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Patent number: 8706788Abstract: A modular calculator and a method of performing a modular calculation are provided. The modular calculator includes a first register to receive and to store a first integer, a second register to receive and to store a second integer, a calculator connected to an output terminal of the first register and an output terminal of the second register, and a controller to determine an arithmetic operation of the calculator by referring to a sign of the first integer and a sign of the second integer and to control the calculator to perform the determined arithmetic operation on one of an addition and a subtraction of the first integer and the second integer and a modulus value.Type: GrantFiled: September 23, 2011Date of Patent: April 22, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Jong Hoon Shin, Kyoung Moon Ahn, Young Sik Kim, Sun-Soo Shin, Ji-Su Kang
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Publication number: 20130262544Abstract: An electronic multiplier, such as a multiplication circuit, may include a partial product generator, a Booth code encoder and an accumulator. The partial product generator may generate partial product data based on a Booth code and multiplicand data. The Booth code encoder may generate the Booth code based on multiplier data. The Booth code may include a zero-generation Booth code and a zero-avoidance Booth code. The Booth code encoder may selectively generate the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero. The accumulator accumulates the partial product data to provide a multiplication result of the multiplicand data and the multiplier data.Type: ApplicationFiled: December 17, 2012Publication date: October 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Ki Lee, Jong-Hoon Shin, Kyoung-Moon Ahn, Ji-Su Kang, Sun-Soo Shin
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Patent number: 8458242Abstract: Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation.Type: GrantFiled: February 25, 2010Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sik Kim, Mi-jung Noh, Kyoung-moon Ahn, Sun-soo Shin
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Patent number: 8407270Abstract: Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.Type: GrantFiled: November 13, 2009Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sik Kim, Mi-jung Noh, Kyoung-moon Ahn, Sun-soo Shin
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Publication number: 20120317159Abstract: A modular operator, a smart card including the same, and a method of operating the same are provided. The modular operator includes: an input unit configured to receive first data, second data, and a modulus; and an accumulator configured to perform an accumulation operation on the first data and a first portion of the second data, to shift the accumulation operation result to the right as much as the number of bits of the first portion, and to perform an accumulation operation on a result of a shifted accumulation operation, a second part, of the second data, which is shifted to the right as much as the number of bits of the first portion, and the modulus.Type: ApplicationFiled: April 20, 2012Publication date: December 13, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Moon Ahn, Jong Hoon Shin, Ji-Su Kang, Sun-Soo Shin
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Publication number: 20120197953Abstract: A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.Type: ApplicationFiled: January 30, 2012Publication date: August 2, 2012Applicant: Samsung Electronics Co., LtdInventors: Young Sik KIM, Kyoung Moon Ahn, Jong Hoon Shin, Sun-Soo Shin, Ji-Su Kang
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Publication number: 20120096062Abstract: A modular calculator and a method of performing a modular calculation are provided. The modular calculator includes a first register to receive and to store a first integer, a second register to receive and to store a second integer, a calculator connected to an output terminal of the first register and an output terminal of the second register, and a controller to determine an arithmetic operation of the calculator by referring to a sign of the first integer and a sign of the second integer and to control the calculator to perform the determined arithmetic operation on one of an addition and a subtraction of the first integer and the second integer and a modulus value.Type: ApplicationFiled: September 23, 2011Publication date: April 19, 2012Applicant: Samsung Electronics Co., LtdInventors: Jong Hoon SHIN, Kyoung Moon AHN, Young Sik KIM, Sun-Soo SHIN, Ji-Su KANG
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Publication number: 20110231467Abstract: A radix-2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the multiplicand, the modulus and the sum, and to divide and to output the received previous sum into units of k bits, an accumulator circuit to receive the partial product, the multiple modulus and k bits of the previous sum from the input coefficient generation unit, and to generate and to output a carry and a sum by summing the partial product, the multiple modulus and the previous sum, and a carry propagation adder (CPA) circuit to generate and to output an ultimate sum by using the carry and the sum.Type: ApplicationFiled: March 21, 2011Publication date: September 22, 2011Applicant: Samsung Electronics Co., LtdInventors: Kyoung-moon AHN, Young-sik Kim, Jong-hoon Shin, Sun-soo Shin, Ji-su Kang
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Patent number: 7965836Abstract: Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.Type: GrantFiled: February 23, 2005Date of Patent: June 21, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-moon Ahn, Mi-jung Noh