Patents by Inventor Kyoung-moon Ahn

Kyoung-moon Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100293216
    Abstract: Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation.
    Type: Application
    Filed: February 25, 2010
    Publication date: November 18, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-sik Kim, Mi-jung Noh, Kyoung-moon Ahn, Sun-soo Shin
  • Publication number: 20100138467
    Abstract: Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.
    Type: Application
    Filed: November 13, 2009
    Publication date: June 3, 2010
    Inventors: Young-sik Kim, Mi-jung Noh, Kyoung-moon Ahn, Sun-soo Shin
  • Patent number: 7606365
    Abstract: A key scheduler, which may selectively generate an encryption round key and a decryption round key corresponding to an initial round key, which may have a variable key length. The key scheduler may include a key storage unit, a key calculating unit, and a key output unit. The key storage unit may receive and store calculation key data items or storage key data items as input key data items, and may output the stored input key data items as the storage key data items. The key calculating unit may output the calculation key data items as the calculation result. The key output unit may select units of the input key data items and the storage key data items in response to output control signals, and may output them as an encryption round key or a decryption round key.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mi-jung Noh, Kyoung-moon Ahn
  • Publication number: 20050207571
    Abstract: Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.
    Type: Application
    Filed: February 23, 2005
    Publication date: September 22, 2005
    Inventors: Kyoung-moon Ahn, Mi-jung Noh
  • Publication number: 20050190923
    Abstract: A key scheduler, which may selectively generate an encryption round key and a decryption round key corresponding to an initial round key, which may have a variable key length. The key scheduler may include a key storage unit, a key calculating unit, and a key output unit. The key storage unit may receive and store calculation key data items or storage key data items as input key data items in response to load enable signals and a clock signal, and may output the stored input key data items as the storage key data items. The key calculating unit may calculate the storage key data items and may output the calculation key data items as the calculation result in response to calculation control signals. The key output unit may select units of the input key data items and the storage key data items in response to output control signals, and may output them as an encryption round key or a decryption round key.
    Type: Application
    Filed: January 11, 2005
    Publication date: September 1, 2005
    Inventors: Mi-Jung Noh, Kyoung-moon Ahn
  • Publication number: 20050169463
    Abstract: A hardware cryptographic engine implementing an Advanced Encryption Standard (AES) algorithm is disclosed. The hardware cryptographic engine comprises a plurality of modules corresponding to rounds of AES. Each of the plurality of modules comprises an S-BOX computing a multiplicative inverse of each element in an input vector over GF(28) using an operation over GF(((22)2)2), and replacing each element of the input vector with a substitute element obtained using a result of the operation.
    Type: Application
    Filed: December 30, 2004
    Publication date: August 4, 2005
    Inventors: Kyoung-moon Ahn, Mi-jung Noh