Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Abstract: Various embodiments of the disclosure provide an apparatus for protecting information. According to various embodiments of the disclosure, an apparatus for monitoring a database includes a transceiver, and a processor operatively coupled to the transceiver. The processor may be configured to acquire a query used in access of the database from the database through the transceiver, replace a first code, included in the acquired query, for query checking to a predefined text, convert the text to a second code for query checking, and output information on validity of the acquired query on the basis of a comparison result of the first code and the second code.

Abstract: A lightened neural network method and apparatus. The neural network apparatus includes a processor configured to generate a neural network with a plurality of layers including plural nodes by applying lightened weighted connections between neighboring nodes in neighboring layers of the neural network to interpret input data applied to the neural network, wherein lightened weighted connections of at least one of the plurality of layers includes weighted connections that have values equal to zero for respective non-zero values whose absolute values are less than an absolute value of a non-zero value. The lightened weighted connections also include weighted connections that have values whose absolute values are no greater than an absolute value of another non-zero value, the lightened weighted connections being lightened weighted connections of trained final weighted connections of a trained neural network whose absolute maximum values are greater than the absolute value of the other non-zero value.

Abstract: A memory system according to the present technology may include a plurality of memory devices including a plurality of memory devices including a plurality of blocks configured of memory cells and a memory controller configured to control the plurality of memory devices corresponding to a plurality of zones by configuring the plurality of zones with the plurality of blocks included in each of the plurality of memory devices, wherein the memory controller is further configured to: receive a write request from a host, determine a target zone indicated by the write request among the plurality of zones, and determine a logical address of the target zone on which a write operation is to be started based on a write pointer and an offset corresponding to the target zone.

Abstract: A bus bar includes terminal portions disposed at both ends, respectively; a plurality of bridges disposed between the terminal portions to electrically connect the terminal portions, and to be sequentially fused when an overcurrent flows. The plurality of bridges may be configured to have different resistance values, respectively.

Abstract: A structure and an operation of a transistor, which is a vertical transistor in which a nanowire-type floating body layer is vertically formed or a horizontal transistor in which a floating body layer is horizontally formed, and implements a spike operation of a neuron by storing and releasing charges inside the transistor, and a neuromorphic system using the same are provided. The vertical transistor includes a floating body layer in a form of a vertical nanowire vertically formed on a substrate, a source and a drain formed above and below the floating body layer, a gate insulating layer formed on the source and surrounding the floating body layer, a gate formed outside the gate insulating layer, and a contact metal being in contact with the source, the drain and the gate to input or output an electrical signal.

Abstract: A power control method of a base station in a wireless communication system based on Orthogonal Frequency Division Multiple Access (OFDMA) is provided for reducing power consumption by turning off the bias of the power amplifier for the duration of a symbol carrying no user data. The method includes checking scheduling information of radio resources, detecting a symbol carrying no user data, based on the scheduling information, and turning off a bias of the power amplifier for a symbol duration of the symbol carrying no user data. The transmission power control method is capable of reducing power consumption of the base station by turning off the bias of the power amplifier of the base station for the symbol duration in which no user data is transmitted.

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

Abstract: A strainer for a fuel pump according to the present invention includes: a communicating pipe including a flow path formed to communicate with a fuel inlet of the fuel pump; a filter including an internal space in which a fuel flows and coupled to the communicating pipe so that the internal space communicates with the communicating pipe; and a rib disposed in the filter and coupled to the communicating pipe, in which the filter includes a first filtering portion extending in a length direction with respect to the communicating pipe, a connecting portion extending in a width direction at an edge of the first filtering portion, and a second filtering portion extending in the length direction at the connecting portion and spaced apart from the first filtering portion in the width direction. Therefore, the strainer may have a relatively large filtering area and a small size.

Abstract: An apparatus and method for detecting a fake fingerprint is disclosed. The apparatus may divide an input fingerprint image into blocks, determine an image quality assessment (IQA) value associated with each block, determine a confidence value based on the IQA values using a confidence determination model, and determine whether an input fingerprint in the input fingerprint image is a fake fingerprint based on the determined confidence value.

Abstract: A battery cell includes a casing having an accommodation space formed therein and having one or both ends open; a cover plate covering one or both open ends of the casing; and an electrode assembly accommodated in the accommodation space, in which a plurality of electrode plates are stacked with a separator interposed therebetween. The electrode assembly includes electrode connection portions, respectively extending from the plurality of electrode plates; and a terminal bonded to the electrode connection portion and having a portion exposed outwardly through the cover plate.

Abstract: Disclosed are a novel rhamnolipid compound, an optical isomer thereof, or a pharmaceutically acceptable salt thereof in the present disclosure. The novel rhamnolipid compound, the optical isomer thereof, or the pharmaceutically acceptable salt thereof selectively exhibits cytotoxicity to human cancer cell lines, thereby inhibiting the growth of cancer cells, and thus has particularly excellent preventive or therapeutic effects against the above-mentioned types of cancers.

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (?) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: A three-dimensional (3D) image-based facial verification method and apparatus is provided. The facial verification method may include capturing a facial image of a 3D face of a user, determining an occluded region in the captured facial image by comparing the captured facial image and an average facial image, generating a synthetic image by synthesizing the captured facial image and the average facial image based on the occluded region, and verifying the user based on the synthetic image.

Abstract: A foldable toy includes: a body part; a support part movably connected to the body part; at least one movable body part movably connected to at least one of the body part or the support part; and a locking part to fix the moveable body part in a first position to lock the foldable toy in a first shape in which the body part, the support part, and the movable body part are deployed. When the locking part is unlocked, the movable body part moves to a second position, and the foldable toy is folded into a second shape in which the body part, the support part, and the movable body part are stacked on one another.

Abstract: A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.

Abstract: A memory system comprising: a plurality of memory devices; a buffer memory suitable for buffering write data inputted from a host; and a controller suitable for: classifying the write data buffered in the buffer memory into N data groups according to logical addresses corresponding to the write data, N being a natural number greater than or equal to 2, selecting at least one data group among the N data groups when a size difference between at least two of the N data groups is equal to or more than a set size, and flushing at least one piece of data of the selected data group to at least one of the plurality of memory devices.

Abstract: A bus bar includes terminal portions disposed at both ends, respectively; a plurality of bridges disposed between the terminal portions to electrically connect the terminal portions, and to be sequentially fused when an overcurrent flows. The plurality of bridges may be configured to have different resistance values, respectively.

Abstract: A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals.