Patents by Inventor Kyu Choi

Kyu Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11946976
    Abstract: An apparatus for measuring an insulation resistance according to the present invention includes: a first distribution resistor connected to a positive terminal of a battery and a ground; a first switch connected to the positive terminal of the battery and the first distribution resistor; a second distribution resistor connected to a negative terminal of the battery and the ground; a second switch connected to the negative terminal of the battery and the second distribution resistor; and an insulation resistance measurement unit measuring a resistance value of a negative electrode insulation resistor of the battery using a first voltage applied to the first distribution resistor and measuring a resistance value of a positive electrode insulation resistor of the battery using a second voltage applied to the second distribution resistor.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 2, 2024
    Assignee: SK ON CO., LTD.
    Inventors: Ho Sang Jang, Seon Yong Kim, Byoung Kyu Park, Yong Sug Choi
  • Patent number: 11948074
    Abstract: Disclosed is a processor-implemented data processing method in a neural network. A data processing apparatus includes at least one processor, and at least one memory configured to store instructions to be executed by the processor and a neural network, wherein the processor is configured to, based on the instructions, input an input activation map into a current layer included in the neural network, output an output activation map by performing a convolution operation between the input activation map and a weight quantized with a first representation bit number of the current layer, and output a quantized activation map by quantizing the output activation map with a second representation bit number based on an activation quantization parameter.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 2, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangil Jung, Changyong Son, Seohyung Lee, Jinwoo Son, Chang Kyu Choi
  • Publication number: 20240103362
    Abstract: Disclosed herein is a method of printing a nanostructure including: preparing a template substrate on which a pattern is formed; forming a replica pattern having an inverse phase of the pattern by coating a polymer thin film on an upper portion of the template substrate, adhering a thermal release tape to an upper portion of the polymer thin film, and separating the polymer thin film from the template substrate; forming a nanostructure by depositing a functional material on the replica pattern; and printing the nanostructure deposited on the replica pattern to a substrate by positioning the nanostructure on the substrate, applying heat and pressure to the nanostructure, and weakening an adhesive force between the thermal release tape and the replica pattern by the heat.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 28, 2024
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jong Min KIM, Seung Yong LEE, So Hye CHO, Ho Seong JANG, Jae Won CHOI, Chang Kyu HWANG
  • Publication number: 20240100464
    Abstract: An air filter comprises: a first filter frame in which a plurality of first chambers are formed; a second filter frame in which a plurality of second chambers are formed and which is arranged at the rear of the first filter frame; and a filter material which is accommodated in the plurality of first chambers and the plurality of second chambers to filter air, wherein the first filter frame and the second filter frame are arranged so that, when seen from the front, the center of each of the plurality of second chambers is out of line with the center of each of the plurality of first chambers, in the vertical direction.
    Type: Application
    Filed: January 28, 2022
    Publication date: March 28, 2024
    Applicant: COWAY CO., LTD.
    Inventors: Yoon Hyuck CHOI, Hyun Kyu LEE, Jong Cheol KIM, Seung Ki KIM, Sung Sil KANG, Ju Hyun BAEK, Chan Jung PARK
  • Patent number: 11939453
    Abstract: A plasticizer composition including a citrate-based material and an epoxidized oil, and the plasticizer composition capable of maintaining an excellent plasticization efficiency and providing an improved mechanical properties and stress resistance when compared with conventional phthalate-based plasticizer products.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: March 26, 2024
    Assignee: LG Chem, Ltd.
    Inventors: Hyun Kyu Kim, Seok Ho Jeong, Jeong Ju Moon, Woo Hyuk Choi
  • Patent number: 11939698
    Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: March 26, 2024
    Assignee: SENIC INC.
    Inventors: Jong Hwi Park, Jung-Gyu Kim, Eun Su Yang, Byung Kyu Jang, Jung Woo Choi, Yeon Sik Lee, Sang Ki Ko, Kap-Ryeol Ku
  • Publication number: 20240092484
    Abstract: A tilt prop aircraft is provided, including a first longeron and a second longeron capable of tilting relatively to each other, a tilt actuator disposed on the second longeron, a first power transmission member rotated by the tilt actuator, a second power transmission member fixed to the first longeron and coupled to the first power transmission member to transmit a rotational movement of the first power transmission member by turning 90 degrees in different planes, a crank fixed to the second longeron and extending through a slot in the first longeron and protruding inwardly from the first longeron, and a connecting rod connected to the crank so as to be relatively rotatable to the crank, and connected to the pitch control rod.
    Type: Application
    Filed: August 15, 2023
    Publication date: March 21, 2024
    Applicant: KOREA AEROSPACE RESEARCH INSTITUTE
    Inventors: Jun Ho CHO, Myeong Kyu LEE, Seong Wook CHOI
  • Publication number: 20240091759
    Abstract: Disclosed herein is a method of depositing a transition metal single-atom catalyst including preparing a carbon carrier, and depositing a transition metal single-atom catalyst on the carbon carrier, in which the carbon carrier is surface-treated by an oxidation process, and wherein the deposition is carried out by an arc plasma process.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jong Min KIM, Sang Hoon KIM, Chang Kyu HWANG, Seung Yong LEE, So Hye CHO, Jae Won CHOI
  • Patent number: 11934950
    Abstract: An apparatus for embedding a sentence feature vector according to an embodiment includes a sentence acquisitor configured to acquire a first sentence and a second sentence, each including one or more words; a vector extractor configured to extract a first feature vector corresponding to the first sentence and a second feature vector corresponding to the second sentence by independently inputting each of the first sentence and the second sentence into a feature extraction network; and a vector compressor configured to compress the first feature vector and the second feature vector into a first compressed vector and a second compressed vector, respectively, by independently inputting each of the first feature vector and the second feature vector into a convolutional neural network (CNN)-based vector compression network.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Seong Ho Joe, Young June Gwon, Seung Jai Min, Ju Dong Kim, Bong Kyu Hwang, Jae Woong Yun, Hyun Jae Lee, Hyun Jin Choi
  • Patent number: 11930361
    Abstract: A method of a wearable device displaying icons is provided. The method includes displaying a plurality of circular icons comprising a first circular icon located in a center area of a touch display in a first size and a second circular icon located outside of the center area of the touch display in a second size smaller than the first size, and based on a direction of a touch input received on the touch display, moving the plurality of circular icons such that the first circular icon is moved to a first position located outside of the center area of the touch display and the second circular icon is moved from a second position located outside the center area of the touch display to the center area of the touch display and enlarged in size from the second size to the first size.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-kyu Seo, Young-joon Choi, Ji-yeon Kwak, Hyun-jin Kim, Yeo-jun Yoon
  • Publication number: 20240076799
    Abstract: A wafer manufacturing method, an epitaxial wafer manufacturing method, and a wafer and epitaxial wafer manufactured thereby, are provided. The wafer manufacturing method enables the manufacture of a wafer with a low density of micropipe defects and minimum numbers of particles and scratches. The epitaxial wafer manufacturing method enables the manufacture of an epitaxial wafer that has low densities of defects such as downfall, triangular, and carrot defects, exhibits excellent device characteristics, and improves the yield of devices.
    Type: Application
    Filed: November 1, 2023
    Publication date: March 7, 2024
    Applicant: SENIC INC.
    Inventors: Jong Hwi PARK, Jung-Gyu KIM, Eun Su YANG, Byung Kyu JANG, Jung Woo CHOI, Yeon Sik LEE, Sang Ki KO, Kap-Ryeol KU
  • Publication number: 20240076604
    Abstract: A large scale bioreactor system includes a stainless steel large scale bioreactor having at least one valve assembly, and an aseptic connector assembly coupled to the at least one valve assembly of the bioreactor. A perfusion device includes an Alternating Tangential Filtration assembly with an autoclaved valve assembly coupled to the aseptic connector assembly, and the aseptic connector assembly includes one of a triclamp aseptic connector or a hose assembly. Single use feed containers include an aseptic connector assembly.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 7, 2024
    Inventors: Gregory S. Stimpfl, Oliver Kaltenbrunner, Mark O. Brothers, David C. Hogenson, Thomsen P. Sawicky, Min Kyu Choi, Jeffrey T. Ranney, John C. Roseland
  • Publication number: 20240075740
    Abstract: An inkjet head unit capable of performing high-resolution pixel printing on a large-size substrate and a substrate treatment apparatus including the inkjet head unit are provided. The substrate treatment apparatus includes: a processing unit supporting and moving a substrate; an inkjet head unit performing pixel printing on the substrate; and a gantry unit moving the inkjet head unit over the substrate, wherein the inkjet head unit includes head packs, which include a plurality of nozzles ejecting a substrate treatment liquid onto the substrate, and a head base, in which the head packs are installed and the head packs are disposed in a single row in the head base.
    Type: Application
    Filed: July 24, 2023
    Publication date: March 7, 2024
    Inventors: Jang Mi WOO, Jin Hyuck Yang, Yong Kyu Cho, Cheon Su Cho, Ki Hoon Choi
  • Patent number: 11925080
    Abstract: A display device includes a substrate including a display area and a non-display area, a plurality of pixels disposed in the display area, a common voltage supply wiring overlapping the non-display area and disposed on the substrate, a driving voltage supply wiring overlapping the non-display area and disposed on the substrate, and a data voltage supply wiring overlapping the non-display area and electrically connected to the plurality of pixels, where at least one of the common voltage supply wiring and the driving voltage supply wiring includes a chamfered area, the data voltage supply wiring includes a first data voltage supply wiring, a second data voltage supply wiring, and a third data voltage supply wiring, and the first to third data voltage supply wirings are disposed in different layers.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae-Ho Choi, Won Kyu Kwak, Chang Soo Pyon, Seung Gyu Tae
  • Patent number: 11922988
    Abstract: Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: March 5, 2024
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yang-Kyu Choi, Myung-Su Kim
  • Publication number: 20240071500
    Abstract: Memory array structures, and methods of their formation, might include a first memory cell having a first control gate and an adjacent first portion of a charge-blocking structure, a second memory cell having a second control gate and an adjacent second portion of the charge-blocking structure, and a first dielectric material between the first control gate and the second control gate, and adjacent to a third portion of the charge-blocking structure that is between the first and second portions of the charge-blocking structure. The third portion of the charge-blocking structure might include a second dielectric material and a third dielectric material different than the second dielectric material, and the first portion of the charge-blocking structure and the second portion of the charge-blocking structure might each include the third dielectric material and a fourth dielectric material different than the second dielectric material. Apparatus might include such memory array structures.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 29, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jae Kyu Choi, Jin Yue, Kyubong Jung, Albert Fayrushin, Jae Young Ahn, Jun Kyu Yang
  • Patent number: 11912120
    Abstract: A battery mounting structure for a vehicle is provided to include a case having a first internal member that is disposed to be spaced parallel to an upper side of a lower panel of the case and a second internal member that is disposed perpendicular to the first internal member, and configured to accommodate a plurality of battery modules therein using the first internal member and the second internal member. An outer side member is provided in a shape protruding toward the outside on an outer side of the case. The battery modules are disposed in a stacking direction of battery cells that is parallel to a longitudinal direction of the first internal member.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 27, 2024
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Yong Hwan Choi, Yu Ri Oh, Tae Hyuck Kim, Gyung Hoon Shin, Hae Kyu Lim, Ji Woong Jung
  • Patent number: 11915432
    Abstract: Disclosed is a target tracking method and apparatus. The target tracking apparatus includes a processor configured to obtain a first depth feature from a target region image and obtain a second depth feature from a search region image, obtain a global response diagram between the first depth feature and the second depth feature, acquire temporary bounding box information based on the global response diagram, updated the second depth feature based on the temporary bounding box information, obtain local feature blocks based on the first depth feature, obtain a local response diagram based on the local feature blocks and the updated second depth feature, and determine output bounding box information based on the local response diagram.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: February 27, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jingtao Xu, Jiaqian Yu, Byung In Yoo, Chang Kyu Choi, Hyunjeong Lee, Hangkai Tan, Jaejoon Han, Qiang Wang, Yiwei Chen
  • Patent number: 11915119
    Abstract: A convolutional neural network (CNN) processing method includes selecting a survival network in a precision convolutional network based on a result of performing a high speed convolution operation between an input and a kernel using a high speed convolutional network, and performing a precision convolution operation between the input and the kernel using the survival network.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 27, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changyong Son, Jinwoo Son, Chang Kyu Choi, Jaejoon Han
  • Patent number: 11901345
    Abstract: A semiconductor package may include: a substrate; a first sub-semiconductor package disposed over the substrate, the first sub-semiconductor package including a first buffer chip and a first memory chip; and a second memory chip disposed over the first sub-semiconductor package, wherein the first buffer chip and the first memory chip are connected to each other using a first redistribution line, and wherein the first buffer chip and the second memory chip are connected to each other using a second bonding wire.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: February 13, 2024
    Assignee: SK hynix Inc.
    Inventors: Jeong Hyun Park, Bok Kyu Choi