Patents by Inventor Kyu-Ha Shim

Kyu-Ha Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220328337
    Abstract: A method of modifying a high-resistivity substrate so that the substrate may be electrostatically clamped to a chuck is disclosed. The bottom surface is implanted with a resistivity-reducing species. In this way, resistivity of the bottom surface of the substrate may be greatly reduced. In some embodiments, to implant the bottom surface, a coating is applied to the top surface. After application of the coating, the substrate is flipped so that the front surface contacts the top surface of the chuck. The ions are then implanted into the exposed bottom surface to create the low resistivity layer. The resistivity of the low resistivity layer proximate the bottom surface after implant may be less than 1000 ohm-cm. Once the bottom surface has been implanted, the substrate may be processed conventionally. The low resistivity layer may later be removed by wafer backside thinning processes.
    Type: Application
    Filed: April 9, 2021
    Publication date: October 13, 2022
    Inventors: Sipeng Gu, Kyu-Ha Shim
  • Publication number: 20220262619
    Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 18, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Ning Li, Shuaidl Zhang, Mihaela A. Balseanu, Qi Gao, Rajesh Prasad, Tomohiko Kitajima, Chang Seok Kang, Deven Matthew Raj Mittal, Kyu-Ha Shim
  • Publication number: 20220109045
    Abstract: A method of isolating sections of the channel layer in a SOI workpiece is disclosed. Rather than etching material to create trenches, which are then filled with a dielectric material, ions are implanted into portions of the channel layer to transform these implanted regions from silicon or silicon germanium into an electrically insulating material. These ions may comprise at least one isolating species, such as oxygen, nitrogen, carbon or boron. This eliminates various processes from the fabrication sequence, including an etching process and a deposition process. Advantageously, this approach also results in greater axial strain in the channel layer, since the channel layer is continuous across the workpiece.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 7, 2022
    Inventors: Sipeng Gu, Wei Zou, Kyu-Ha Shim
  • Publication number: 20220102500
    Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Sipeng Gu, Wei Zou, Kyu-Ha Shim, Qintao Zhang
  • Patent number: 11114299
    Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 7, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Kyu-Ha Shim, Rajesh Prasad
  • Patent number: 10930508
    Abstract: Disclosed are methods of forming devices. One method may include providing a first set of fins and a second set of fins extending from a substrate, and providing a dummy oxide over the first set of fins and the second set of fins. The method may further include performing a thermal implant to the second set of fins, wherein the thermal implant is an angled ion implant impacting the dummy oxide. The method may further include removing the dummy oxide from the first set of fins and the second set of fins, and forming a first work function (WF) metal over the first set of fins and a second WF metal over the second set of fins.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Kyu-Ha Shim
  • Publication number: 20210005445
    Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 7, 2021
    Applicant: APPLIED Materials, Inc.
    Inventors: Qintao Zhang, Kyu-Ha Shim, Rajesh Prasad
  • Patent number: 10811257
    Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 20, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-Ha Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
  • Publication number: 20200273707
    Abstract: Disclosed are methods of forming devices. One method may include providing a first set of fins and a second set of fins extending from a substrate, and providing a dummy oxide over the first set of fins and the second set of fins. The method may further include performing a thermal implant to the second set of fins, wherein the thermal implant is an angled ion implant impacting the dummy oxide. The method may further include removing the dummy oxide from the first set of fins and the second set of fins, and forming a first work function (WF) metal over the first set of fins and a second WF metal over the second set of fins.
    Type: Application
    Filed: September 4, 2019
    Publication date: August 27, 2020
    Applicant: APPLIED Materials, Inc.
    Inventors: Qintao Zhang, Kyu-Ha Shim
  • Publication number: 20190304783
    Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 3, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-HA Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
  • Patent number: 10354875
    Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: July 16, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Ning Zhan, Tzu-Yu Liu, James Cournoyer, Kyu-Ha Shim, Kwangduk Lee, John Lee Klocke, Eric J. Bergman, Terrance Lee, Harry S. Whitesell
  • Publication number: 20190214255
    Abstract: A method may include forming a sacrificial mask on a device structure, the sacrificial mask comprising a carbon-based material. The method may further include etching memory structures in exposed regions of the sacrificial mask, implanting an etch-enhancing species into the sacrificial mask, and performing a wet etch to selectively remove the sacrificial mask at etch temperature, less than 350° C.
    Type: Application
    Filed: April 6, 2018
    Publication date: July 11, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Ning Zhan, Tzu-Yu Liu, James Cournoyer, Kyu-Ha Shim, Kwangduk Lee, John Lee Klocke, Eric J. Bergman, Terrance Lee, Harry S. Whitesell
  • Patent number: 10332748
    Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: June 25, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
  • Patent number: 10204909
    Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 12, 2019
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
  • Publication number: 20180182636
    Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.
    Type: Application
    Filed: February 21, 2018
    Publication date: June 28, 2018
    Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
  • Patent number: 9934982
    Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: April 3, 2018
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
  • Publication number: 20170178914
    Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
  • Publication number: 20170179133
    Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
  • Patent number: 8716155
    Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deepak A. Ramappa, Kyu-Ha Shim
  • Publication number: 20130005155
    Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATE, INC.
    Inventors: Deepak RAMAPPA, Kyu-Ha SHIM