Patents by Inventor Kyu-Ha Shim
Kyu-Ha Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180182636Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.Type: ApplicationFiled: February 21, 2018Publication date: June 28, 2018Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
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Patent number: 9934982Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.Type: GrantFiled: December 21, 2015Date of Patent: April 3, 2018Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
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Publication number: 20170179133Abstract: Provided herein are approaches for forming a gate oxide layer for a DRAM device, the method including providing a finned substrate having a recess formed therein, and performing an ion implant into a sidewall surface of the recess to form a gate oxide layer having a non-uniform thickness, wherein a thickness of the gate oxide layer at a top section of the sidewall surface is greater than a thickness of the gate oxide layer at a bottom section of the sidewall surface. In some approaches, the ion implant is provided as a series of ion implants at multiple different implant angles, varied along with an ion implantation energy and/or an ion dose to increase the thickness of the gate oxide of the top section of the sidewall surface. In some approaches, the finned substrate is also exposed to a plasma, either during or after, the ion implantation.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Simon Ruffell, Arvind Kumar, Tristan Ma, Kyu-Ha Shim, John Hautala, Steven Sherman
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Publication number: 20170178914Abstract: As etching processes become more aggressive, increased etch resistivity of the hard mask is desirable. Methods of modulating the etch rate of the mask and optionally the underlying material are disclosed. An etch rate modifying species is implanted into the hard mask after the mask etching process is completed. This etch rate modifying species increases the difference between the etch rate of the mask and the etch rate of the underlying material to help preserve the integrity of the mask during a subsequent etching process. In some embodiments, the etch rate of the mask is decreased by the etch rate modifying species. In certain embodiments, the etch rate of the underlying material is increased by the etch rate modifying species.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Inventors: Rajesh Prasad, Steven Robert Sherman, Andrew M. Waite, Sungho Jo, Kyu-Ha Shim, Guy Oteri, Somchintana Norasetthekul
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Patent number: 8716155Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: GrantFiled: September 11, 2012Date of Patent: May 6, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak A. Ramappa, Kyu-Ha Shim
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Publication number: 20130005155Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATE, INC.Inventors: Deepak RAMAPPA, Kyu-Ha SHIM
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Patent number: 8283265Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: GrantFiled: December 17, 2009Date of Patent: October 9, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Deepak Ramappa, Kyu-Ha Shim
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Patent number: 8012843Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.Type: GrantFiled: August 5, 2010Date of Patent: September 6, 2011Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
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Patent number: 7993698Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise at least one thermal sensor adapted to measure a temperature of a wafer during an ion implantation process inside an end station of an ion implanter. The apparatus may also comprise a thermal conditioning unit coupled to the end station. The apparatus may further comprise a controller in communication with the thermal sensor and the thermal conditioning unit, wherein the controller compares the measured temperature to a desired wafer temperature and causes the thermal conditioning unit to adjust the temperature of the wafer based upon the comparison.Type: GrantFiled: September 23, 2006Date of Patent: August 9, 2011Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Julian Blake, Jonathan England, Scott Holden, Steven R. Walther, Reuel Liebert, Richard S. Muka, Ukyo Jeong, Jinning Liu, Kyu-Ha Shim, Sandeep Mehta
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Publication number: 20110034014Abstract: A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained.Type: ApplicationFiled: August 4, 2010Publication date: February 10, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Jay T. Scheuer
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Publication number: 20110033998Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.Type: ApplicationFiled: August 5, 2010Publication date: February 10, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Christopher R. Hatem, Benjamin Colombeau, Thirumal Thanigaivelan, Kyu-Ha Shim, Dennis Rodier
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Publication number: 20100155909Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.Type: ApplicationFiled: December 17, 2009Publication date: June 24, 2010Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Deepak RAMAPPA, Kyu-Ha SHIM
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Publication number: 20080076194Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise at least one thermal sensor adapted to measure a temperature of a wafer during an ion implantation process inside an end station of an ion implanter. The apparatus may also comprise a thermal conditioning unit coupled to the end station. The apparatus may further comprise a controller in communication with the thermal sensor and the thermal conditioning unit, wherein the controller compares the measured temperature to a desired wafer temperature and causes the thermal conditioning unit to adjust the temperature of the wafer based upon the comparison.Type: ApplicationFiled: September 23, 2006Publication date: March 27, 2008Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Julian Blake, Jonathan England, Scott Holden, Steven R. Walther, Reuel Liebert, Richard S. Muka, Ukyo Jeong, Jinning Liu, Kyu-Ha Shim, Sandeep Mehta
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Publication number: 20060258128Abstract: Substrate masking apparatus includes a platen assembly to support a substrate for processing, a mask having an aperture, a retaining mechanism to retain the mask in a masking position, and a positioning mechanism to change the relative positions of the mask and the substrate so that different areas of the substrate are exposed through the aperture in the mask. The apparatus may further include a mask loading mechanism to transfer the mask to and between the masking position and a non-masking position. The processing may include ion implantation of the substrate with different implant parameter values in different areas. In other embodiments, an area of the substrate to be processed is selectable by a mask, a shutter or a beam modifier in front of the substrate.Type: ApplicationFiled: January 11, 2006Publication date: November 16, 2006Inventors: Peter Nunan, Anthony Renau, Alan Sheng, Paul Murphy, Kyu-Ha Shim, Charles Teodorczyk, Steven Anella, Samuel Barsky, Lawrence Ficarra, Richard Hertel