Patents by Inventor Kyu-hee Han

Kyu-hee Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566284
    Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Kwan Kim, Sanghoon Ahn, Kyu-Hee Han, JaeWha Park, Heesook Park
  • Publication number: 20200051909
    Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.
    Type: Application
    Filed: February 26, 2019
    Publication date: February 13, 2020
    Inventors: Ji Young KIM, Kyu Hee HAN, Sung Bin PARK, Yeong Gil KIM, Jong Min BAEK, Kyoung Woo LEE, Deok Young JUNG
  • Publication number: 20200035515
    Abstract: A cleaning solution production system is for cleaning a semiconductor substrate. The system includes a pressure tank, a plasma reaction tank configured to form a plasma in gas bubbles suspended in a decompressed liquid obtained from the pressure tank to thereby generate radical species in the decompressed liquid, a storage tank configured to store a cleaning solution containing the radical species generated in the plasma reaction tank, and a nozzle configured to supply the cleaning solution from the storage tank to a semiconductor substrate.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 30, 2020
    Inventors: Beom Jin YOO, Min Hyoung KIM, Sang Ki NAM, Won Hyuk JANG, Kyu Hee HAN, Young Do KIM, Jeong Min BANG
  • Publication number: 20200020551
    Abstract: A plasma generator, a cleaning liquid processing apparatus including the same, a semiconductor cleaning apparatus, and a cleaning liquid processing method are provided. The cleaning liquid processing apparatus comprising a bubble formation section configured to lower a pressure of a mixed liquid obtained by mixing a liquid and a gas to form bubbles in the mixed liquid, a plasma generator connected to the bubble formation section and configured to apply a voltage to the mixed liquid to form plasma in the bubbles formed in the mixed liquid, a mixing section connected to the plasma generator and configured to dissolve radicals included in the plasma into the mixed liquid, and a discharge nozzle connected to the mixing section and configured to discharge the mixed liquid to a wafer.
    Type: Application
    Filed: May 24, 2019
    Publication date: January 16, 2020
    Inventors: Beom Jin YOO, Min Hyoung KIM, Sang Ki NAM, Lu SIQING, Won Hyuk JANG, Kyu Hee HAN
  • Patent number: 10446495
    Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonhee Kang, Jiyoung Kim, Taejin Yim, Jongmin Baek, Sanghoon Ahn, Hyeoksang Oh, Kyu-Hee Han
  • Publication number: 20190287792
    Abstract: A method of manufacturing an integrated circuit (IC) device includes exposing a partial region of a photoresist film formed on a main surface of a substrate to generate acid, and diffusing the acid in the partial region of the photoresist film. Diffusing the acid may include applying an electric field, in a direction perpendicular to a direction in which the main surface of the substrate extends, to the photoresist film using an electrode facing the substrate through an electric-field transmission layer filling between the photoresist film and the electrode. The electric-field transmission layer may include an ion-containing layer or a conductive polymer layer.
    Type: Application
    Filed: October 19, 2018
    Publication date: September 19, 2019
    Applicant: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Jin PARK, Sang Ki NAM, Kyu-hee HAN, Jin-ok KIM, Jin-hong PARK, Gwang-we YOO
  • Patent number: 10304734
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Publication number: 20190157214
    Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.
    Type: Application
    Filed: July 5, 2018
    Publication date: May 23, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun Kwan KIM, Sanghoon AHN, Kyu-Hee HAN, JaeWha PARK, Heesook PARK
  • Publication number: 20190139813
    Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 9, 2019
    Inventors: Sang-Shin JANG, Woo-Kyung YOU, Kyu-Hee HAN, Jong-Min BAEK, Viet Ha NGUYEN, Byung-Hee KIM
  • Publication number: 20190043809
    Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.
    Type: Application
    Filed: March 1, 2018
    Publication date: February 7, 2019
    Inventors: Yoonhee KANG, Jiyoung Kim, Taejin Yim, Jongmin Baek, Sanghoon Ahn, Hyeoksang Oh, Kyu-Hee Han
  • Patent number: 10199263
    Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Shin Jang, Woo-Kyung You, Kyu-Hee Han, Jong-Min Baek, Viet Ha Nguyen, Byung-Hee Kim
  • Patent number: 10196738
    Abstract: Provided are a deposition process monitoring system capable of detecting an internal state of a chamber in a deposition process, and a method of controlling the deposition process and a method of fabricating a semiconductor device using the system.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-yun Lee, Ju-hyun Lee, Kee-soo Park, Kyu-hee Han, Seung-hun Lee, Byung-chul Jeon
  • Publication number: 20180330987
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: WOO KYUNG YOU, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
  • Publication number: 20180320267
    Abstract: A gas injection apparatus, which can sequentially supply a substrate with at least two kinds of source gases reacting with each other in a container, and thin film deposition equipment including the gas injection apparatus, are provided. The gas injection apparatus includes a base plate, a first gas supply region protruding from the base plate, a second gas supply region protruding from the base plate and adjacent the first gas supply region, and a trench defined by a sidewall of the first gas supply region and a sidewall of the second gas supply region. The sidewall of the first gas supply region and the sidewall of the second gas supply region face each other and extend in a radial direction on the base plate.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Ki-Chul Kim, Jung-Il Ahn, Jung-Hun Seo, Jong-Cheol Lee, Kyu-Hee Han, Seung-Han Lee, Jin-Pil Heo
  • Patent number: 10090381
    Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongmin Baek, Vietha Nguyen, Wookyung You, Sangshin Jang, Byunghee Kim, Kyu-Hee Han
  • Patent number: 10062609
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Patent number: 10041172
    Abstract: A gas injection apparatus, which can sequentially supply a substrate with at least two kinds of source gases reacting with each other in a container, and thin film deposition equipment including the gas injection apparatus, are provided. The gas injection apparatus includes a base plate, a first gas supply region protruding from the base plate, a second gas supply region protruding from the base plate and adjacent the first gas supply region, and a trench defined by a sidewall of the first gas supply region and a sidewall of the second gas supply region. The sidewall of the first gas supply region and the sidewall of the second gas supply region face each other and extend in a radial direction on the base plate.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Chul Kim, Jung-Il Ahn, Jung-Hun Seo, Jong-Cheol Lee, Kyu-Hee Han, Seung-Han Lee, Jin-Pil Heo
  • Publication number: 20180130697
    Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.
    Type: Application
    Filed: June 7, 2017
    Publication date: May 10, 2018
    Inventors: Sang-Shin JANG, Woo-Kyung YOU, Kyu-Hee HAN, Jong-Min BAEK, Viet Ha NGUYEN, Byung-Hee KIM
  • Publication number: 20180096880
    Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.
    Type: Application
    Filed: June 2, 2017
    Publication date: April 5, 2018
    Inventors: Kyu Hee HAN, Jong Min BAEK, Viet Ha NGUYEN, Woo Kyung YOU, Sang Shin JANG, Byung Hee KIM
  • Publication number: 20180083099
    Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.
    Type: Application
    Filed: June 21, 2017
    Publication date: March 22, 2018
    Inventors: JONGMIN BAEK, VIETHA NGUYEN, WOOKYUNG YOU, Sangshin JANG, BYUNGHEE KIM, Kyu-Hee HAN