Abstract: A semiconductor device includes a substrate, a gate electrode disposed on an upper surface of the substrate, a source region disposed on a first side of the gate electrode, a drain region disposed on a second side of the gate electrode opposite to the first side of the gate electrode in a horizontal direction, and an insulating structure at least partially buried inside the substrate on the substrate. The insulating structure includes a first portion disposed between the substrate and the gate electrode, and a second portion in contact with the drain region. An uppermost surface of the second portion of the insulating structure is lower than an uppermost surface of the first portion of the insulating structure. At least a part of the gate electrode is disposed on the uppermost surface of the second portion of the insulating structure.

Abstract: An electrode assembly, a battery, a battery pack and a vehicle including the same are provided. The first electrode of the electrode assembly includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction, the first uncoated portion includes a plurality of segments independently bendable along the winding direction and exposed beyond a the separator of the electrode assembly, the plurality of segments are aligned along a radial direction of the electrode assembly to define a plurality of segment alignments spaced apart in a circumferential direction of the electrode assembly, and an electrolyte impregnation portion in which an end of the first active material portion is exposed between winding turns of the separator is included between adjacent segment alignments of the first uncoated portion in the circumferential direction.

Abstract: Discussed is a battery including an electrode assembly having a first electrode, a second electrode and a separator between the first electrode and the second electrode, a battery housing having a first end with a first opening and a second end with a second opening opposite the first end, the battery housing accommodating the electrode assembly and electrically connected to the second electrode to have a second polarity, a terminal electrically connected to the first electrode to have a first polarity, the terminal being exposed out of the battery housing through the first opening of the battery housing at the first end, and a cap covering and sealing the second opening at the second end of the battery housing. The cap overlaps the battery housing at the second end and has no polarity.

Abstract: A pixel circuit can include a driving element connected to a first node, a second node and a third node; a first switch element supplying an initialization voltage to the second node; a second switch element supplying a data voltage to a fourth node; and a capacitor connected between the third node and the fourth node. Also, the pixel circuit can further include a third switch element supplying a reference voltage to the third node; a fourth switch element supplying a pixel driving voltage to the first node; a fifth switch element electrically connecting the fourth node with the second node; a light emitting element driven to emit light based on a current supplied through the driving element; and a sixth switch element configured to electrically connect the third node with a fifth node connected to an anode electrode of the light emitting element.

Abstract: The present invention relates to a DNA-peptide complex with a high-density functional group, a DNA-peptide-nanomaterial complex and a method for production of the same, a DNA-metal nanowire, and a method for production of the same. The DNA-peptide complex with a high-density functional group may include a DNA molecule; and a peptide containing an amino acid sequence capable of binding to the DNA molecule, wherein the peptide contains at least one functional group at a terminal thereof, wherein the peptide binds to the DNA molecule via at least one of electrostatic interaction, intercalation, and groove binding.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Abstract: Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A main Insulated Gate Bipolar Transistor (IGBT) and a sense IGBT may have a sense resistor connected between a sense emitter of the sense IGBT and a main emitter of the main IGBT. Back-to-back Zener diodes may be connected between a sense gate of the sense IGBT and the sense emitter, and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event.

Abstract: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.

Abstract: A method includes providing a first electrode and a second electrode, receiving a first plurality of signals from the first electrode during a first period of time, and receiving a second plurality of signals from the second electrode during a second period of time. The method also includes receiving a pooled signal comprising a third plurality of signals from the first electrode and a fourth plurality of signals from the second electrode and isolating, from the pooled signal, one or more of the third plurality of signals and one or more of the fourth plurality of signals.

Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

Abstract: A main Insulated Gate Bipolar Transistor (IGBT) and a sense IGBT may have a sense resistor connected between a sense emitter of the sense IGBT and a main emitter of the main IGBT. Back-to-back Zener diodes may be connected between a sense gate of the sense IGBT and the sense emitter, and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event.

Abstract: A power device, which has a Field Stop (FS) layer based on a semiconductor substrate between a collector region and a drift region in an FS-IGBT structure. The FS layer includes multiple implants for improved functionality of the power device.

Abstract: A Hunter syndrome therapeutic agent contains a first composition to be intravenously injected and a second composition to be subcutaneously injected. The agent can reduce the number of visits to the hospital by patients with Hunter syndrome to twice a month or less. It maintains a medicinal effect equivalent to or greater than that of a conventional once-a-week IV injection, increases drug-taking compliance of patients in comparison to conventional therapeutic agents and treatment methods, and enables enhanced patient welfare and convenience.

Abstract: A Hunter syndrome therapeutic agent contains a first composition to be intravenously injected and a second composition to be subcutaneously injected. The agent can reduce the number of visits to the hospital by patients with Hunter syndrome to twice a month or less. It maintains a medicinal effect equivalent to or greater than that of a conventional once-a-week IV injection, increases drug-taking compliance of patients in comparison to conventional therapeutic agents and treatment methods, and enables enhanced patient welfare and convenience.

Abstract: In one general aspect, a power device can include a first Field Stop (FS) layer of a first conductivity type formed from a first-conductive-type semiconductor substrate. The first FS layer can include a first region having a constant impurity density profile along a depth direction and a second region having an impurity density profile along the depth direction lower than the impurity density profile of the first region. The power device can include a second FS layer of the first conductivity type disposed on a first surface of the first FS layer. The second FS layer can include a first implanted FS layer having an impurity density higher than an impurity density of the first FS layer, and a second implanted FS layer having an impurity density lower than the first implanted FS layer. The second implanted FS layer can be disposed between the first FS layer and the first implanted FS layer. The power device can include a transistor device having components disposed on the second FS layer.

Abstract: A Hunter syndrome therapeutic agent contains a first composition to be intravenously injected and a second composition to be subcutaneously injected. The agent can reduce the number of visits to the hospital by patients with Hunter syndrome to twice a month or less. It maintains a medicinal effect equivalent to or greater than that of a conventional once-a-week IV injection, increases drug-taking compliance of patients in comparison to conventional therapeutic agents and treatment methods, and enables enhanced patient welfare and convenience.