Abstract: In one general aspect, a method of fabricating a power device can include preparing a semiconductor substrate of a first conductivity type, and forming a first Field Stop (FS) layer and a second FS layer.

Abstract: A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area.

Abstract: A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area.

Abstract: In a general aspect, a power semiconductor device can include a substrate having a first surface and a second surface. The substrate can include at least one uneven portion defined on the second surface. The device can include a gate electrode and an emitter electrode disposed on the first surface of the substrate. A collector region of the device can be defined on at least a part of the at least one uneven portion. The device can also include a buffer layer disposed in the substrate.

Abstract: Provided are a power device having an improved field stop layer and a method of manufacturing the same. The power device includes: a first field stop layer formed of a semiconductor substrate and of a first conductive type; a second field stop layer formed on the first field stop layer and of the first conductive type, the second field stop layer having a region with an impurity concentration higher than the first field stop layer; a drift region formed on the second field stop layer and of the first conductive type, the drift region having an impurity concentration lower than the first field stop layer; a plurality of power device cells formed on the drift region; and a collector region formed below the first field stop layer, wherein the second field stop layer includes a first region having a first impurity concentration and a second region having a second impurity concentration higher than the first impurity concentration.

Abstract: A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

Abstract: A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

Abstract: A power device, which has a Field Stop (FS) layer based on a semiconductor substrate between a collector region and a drift region in an FS-IGBT structure, wherein the thickness of the FS layer and the impurity density of the collector region are easy to adjust and the FS layer has an improved function, and a fabricating method thereof.

Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.

Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.

Abstract: Provided is a high-voltage semiconductor device which is constructed such that the quantity of P and N charges are balanced in the entire drift region thereby preventing the degradation of the device breakdown characteristics. The high-voltage semiconductor device comprises an active region including N pillars of N conductivity type and P pillars of P conductivity type, arranged alternately in a direction from a center portion of the active region to an outer portion thereof to encircle each other in a horizontal direction. The N and P pillars are formed in a closed shape.

Abstract: In one embodiment, a semiconductor device includes a plurality of fin-shaped active regions defined by a trench formed in a substrate with a predetermined depth; an isolation layer formed inside the trench and comprising a first insulating material; and a plurality of word lines formed on the isolation layer inside the trench and covering a sidewall of the active region inside the trench. A separation layer is formed between two neighboring word lines to separate the two neighboring word lines of the plurality of word lines inside the trench with a predetermined distance. The separation layer comprises a second insulating material having an etch selectivity with respect to the first insulating material.

Abstract: Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Abstract: Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Abstract: The present invention relates to a composition comprising itraconazole for oral administration, more precisely, a composition for oral administration containing 1 part by weight itraconazole, 0.1-0.5 part by weight citric acid and 0.1-0.5 part by weight hydroxypropylmethylcellulose. The composition of the present invention has the advantages of mitigating discomfort of administration by reducing the amount of the additives used to make itraconazole water-soluble, lowering the production price by shortening processing time of spray-drying, high solubility and dissolution rate, excellent reproducibility and stability.

Abstract: An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.

Abstract: Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an electrically conductive lower barrier layer that lines at least an upper portion of a sidewall of the contact hole. This lower barrier layer may comprise titanium nitride (TiN). A step is also performed to form an electrically conductive contact plug that extends in the contact hole, is electrically coupled to the lower barrier layer and protrudes above the electrically insulating layer. The contact plug may comprise tungsten (W). An electrically conductive upper barrier layer is then formed that extends on a protruded upper surface of the contact plug and on a surface of the lower barrier layer.

Abstract: Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Abstract: A DRAM device in which a portion of bit lines has enlarged width portions at a portion of a peripheral/core area to be connected with upper layered circuit wiring through metal contacts, includes spacers formed of a layer of material having an etch selectivity with respect to a bit line interlayer insulating layer deposited after said bit lines are formed, and disposed on sides of an upper surface of each said enlarged width portion to protect sides of said enlarged width portions; an interlayer insulating layer and at least a portion of an etch stop layer disposed between said bit lines and transistors of a substrate; and metal contact pads formed along with bit line contact plugs to pass through said interlayer insulating layer and said etch stop layer.

Abstract: An integrated circuit memory device is formed by forming an interlevel insulating layer on a substrate. A plurality of storage node contact holes are formed in the interlayer insulating layer and are arranged in a pattern. A plurality of contact plugs are formed in the plurality of storage node contact holes, respectively. A material layer is formed on the interlevel insulating layer that has a plurality of landing pad holes that expose the plurality of contact plugs, respectively, the plurality of landing pad holes are arranged in a pattern that is offset with respect to the pattern of the storage node contact holes. A plurality of landing pads are formed in the plurality of landing pad holes and are connected to the plurality of contact plugs, respectively. A plurality of storage nodes are formed that are connected to the plurality of landing pads, respectively.