Patents by Inventor KYU OH

KYU OH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9958603
    Abstract: An optical fiber for an optical fiber sensor and a chemical sensor using the same are disclosed. The optical fiber includes a core area, and a suspended cladding area formed around the core area and having at least one cladding hole. The core area has at least one core hole for reducing an effective refractive index of the core area. The optical fiber and the chemical sensor using the same may have improved measurement sensitivity by increasing an evanescent field fraction of existing suspended core fibers.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 1, 2018
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Bok Hyeon Kim, Youngjoo Chung, So Eun Kim, Bongkyun Kim, Tae Joong Eom, Myoung Kyu Oh
  • Publication number: 20180105494
    Abstract: The present invention provides an N1-cyclic amine-N5-substituted biguanide derivative compound represented by Formula 1, a method of preparing the same and a pharmaceutical composition including the biguanide derivative or the pharmaceutically acceptable salt thereof as an active ingredient. The biguanide derivatives have an effect of inhibiting cancer cell proliferation, cancer metastasis and cancer recurrence by activation of AMPK, even when administered in a small dose compared with conventional drugs.
    Type: Application
    Filed: December 14, 2017
    Publication date: April 19, 2018
    Inventors: Chang Hee MIN, Yong Eun KIM, Byung Kyu OH, Ji Sun LEE, Hye Jin HEO, Ju Hoon OH, Woong CHO
  • Patent number: 9947631
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kyu-Oh Lee
  • Publication number: 20180076119
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 15, 2018
    Inventors: Sri Chaitra J. Chavali, Amanda E. Schuckman, Kyu Oh Lee
  • Publication number: 20180076161
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 15, 2018
    Inventors: Rahul Jain, Kyu Oh Lee, Amanda E. Schuckman, Steve S. Cho
  • Patent number: 9917044
    Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Zheng Zhou, Mihir K. Roy, Chong Zhang, Kyu-Oh Lee, Amanda E. Schuckman
  • Patent number: 9884821
    Abstract: The present invention provides an N1-cyclic amine-N5-substituted biguanide derivative compound represented by Formula 1, a method of preparing the same and a pharmaceutical composition including the biguanide derivative or the pharmaceutically acceptable salt thereof as an active ingredient. The biguanide derivatives have an effect of inhibiting cancer cell proliferation, cancer metastasis and cancer recurrence by activation of AMPK, even when administered in a small dose compared with conventional drugs.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: February 6, 2018
    Assignee: ImmunoMet Therapeutics Inc.
    Inventors: Chang Hee Min, Yong Eun Kim, Byung Kyu Oh, Ji Sun Lee, Hye Jin Heo, Ju Hoon Oh, Woong Cho
  • Publication number: 20180019219
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
    Type: Application
    Filed: February 25, 2015
    Publication date: January 18, 2018
    Applicant: INTEL CORPORATION
    Inventors: Srinivas V. Pietambaram, Kyu Oh Lee
  • Patent number: 9865568
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Publication number: 20170358528
    Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.
    Type: Application
    Filed: June 13, 2016
    Publication date: December 14, 2017
    Inventors: Kristof Kuwawi Darmawikarta, Kyu Oh Lee, Daniel Nicholas Sobieski
  • Patent number: 9837341
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Sri Chaitra J. Chavali, Amanda E. Schuckman, Kyu Oh Lee
  • Patent number: 9837437
    Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
  • Patent number: 9830415
    Abstract: A method of designing a semiconductor integrated circuit (IC) is provided as follows. A standard cell library is generated. The standard cell library includes characteristic information for a plurality of standard cells. The characteristic information includes a characteristic of each standard cell. A characteristic change region is detected. The characteristic change region includes at least one of the plurality of standard cells by comparing characteristics of standard cells to be placed adjacent to the characteristic change region, based on the standard cell library. A characteristic of the at least one standard cell included in the detected characteristic change region is changed to one of the characteristics of the standard cells to be placed adjacent to the characteristic change region to update the standard cell library. A plurality of standard cells of the updated standard cell library is placed.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-kyu Oh, Sang-hoon Baek, Seung-young Lee, Tae-joong Song
  • Publication number: 20170335358
    Abstract: The present invention relates to a mutant microorganism in which a gene that encodes phosphofructokinase-2 is disrupted or deleted to reduce glycolytic flux to thereby improve the ability of the microorganism to produce N-acetylglucosamine, and to a method of producing N-acetylglucosamine using the mutant microorganism. The mutant microorganism according to the present invention has advantages in that it has high resistance to various chemical substances, grows rapidly, is easily cultured, and produces N-acetylglucosamine with high efficiency, indicating that it is useful for production of a large amount of N-acetylglucosamine.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 23, 2017
    Inventors: Min-Kyu Oh, Sang-Woo Lee
  • Publication number: 20170318669
    Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 2, 2017
    Inventors: Kristof Darmawikarta, Daniel Sobieski, Kyu Oh Lee, Sri Ranga Sai Boyapati
  • Patent number: 9791470
    Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Feras Eid, Sasha N. Oster, Kyu Oh Lee, Sarah Haney
  • Publication number: 20170271367
    Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.
    Type: Application
    Filed: June 2, 2017
    Publication date: September 21, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon BAEK, Sang-kyu OH, Jung-Ho DO, Sun-young PARK, Seung-young LEE, Hyo-sig WON
  • Publication number: 20170271264
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: September 19, 2014
    Publication date: September 21, 2017
    Inventor: Kyu-Oh LEE
  • Patent number: 9719456
    Abstract: A method for controlling an engine in various operating modes and for controlling an engine having dual injectors, may include selecting a number of injectors configured to inject fuel based on an operating mode of the various operating modes, and injecting fuel based on a selection of whether to inject fuel while an intake valve is open, or to inject fuel while the intake valve is closed.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 1, 2017
    Assignees: Hyundai Motor Company, KIA Motors Corporation
    Inventor: Young Kyu Oh
  • Patent number: 9716106
    Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won