Patents by Inventor KYU OH

KYU OH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200005994
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Kyu-Oh LEE, Rahul JAIN, Sai VADLAMANI, Cheng XU, Ji Yong PARK, Junnan ZHAO, Seo Young KIM
  • Publication number: 20200008302
    Abstract: A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Rahul JAIN, Prithwish CHATTERJEE, Kyu-oh LEE
  • Publication number: 20190393217
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Application
    Filed: May 3, 2019
    Publication date: December 26, 2019
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20190385780
    Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Publication number: 20190385959
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Application
    Filed: June 19, 2018
    Publication date: December 19, 2019
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Publication number: 20190373736
    Abstract: Described herein are systems and methods for creating a cavity within a substrate. The systems and methods may include passing a plasma gas over a first surface of the substrate. The plasma gas may include a reactant gas. The systems and methods also may include removing a portion of the substrate by reacting the reactant gas with a constituent of the first surface of the substrate, thereby forming the cavity.
    Type: Application
    Filed: March 31, 2017
    Publication date: December 5, 2019
    Inventors: Rahul Jain, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani
  • Publication number: 20190355654
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.
    Type: Application
    Filed: May 21, 2018
    Publication date: November 21, 2019
    Applicant: Intel Corporation
    Inventors: Cheng Xu, Jiwei Sun, Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown
  • Publication number: 20190355675
    Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: Kyu-Oh LEE, Sai VADLAMANI, Rahul JAIN, Junnan ZHAO, Ji Yong PARK, Cheng XU, Seo Young KIM
  • Patent number: 10468352
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventor: Kyu-Oh Lee
  • Patent number: 10468374
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Publication number: 20190322912
    Abstract: The present disclosure relates to an acrylic adhesive composition exhibiting excellent lap shear strength and adhesive strength by including an adhesion enhancer of a specific component.
    Type: Application
    Filed: May 2, 2018
    Publication date: October 24, 2019
    Applicant: LG Chem, Ltd.
    Inventors: Wan Kyu Oh, Gyeong Shin Choi, Seung Young Park
  • Patent number: 10446500
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventor: Kyu-Oh Lee
  • Publication number: 20190300754
    Abstract: A two-component adhesive composition includes: (i) a first part of a (meth)acrylate-based monomer mixture including components (a1) to (a3) below: (a1) an alkyl (meth)acrylate compound, and any one or more of a (meth)acrylate compound having an alkoxysilyl group, and a (meth)acrylate compound having an unsaturated functional group except for an acryloyl group, (a2) 50 to 100 parts by weight of an adhesive reinforcing agent relative to the 100 parts by weight of the (meth)acrylate-based monomer mixture, and (a3) 1 to 10 parts by weight of a filler relative to the 100 parts by weight of the (meth)acrylate-based monomer mixture; and (ii) a second part including components (b1) and (b2) below with a weight ratio of 1:1 to 20:1, where (b1) 100 parts by weight of an epoxy resin, and (b2) 50 to 150 parts by weight of an initiator with respect to (b1).
    Type: Application
    Filed: May 25, 2018
    Publication date: October 3, 2019
    Applicant: LG Chem, Ltd.
    Inventors: Wan Kyu Oh, Gyeong Shin Choi, Seung Young Park
  • Publication number: 20190304933
    Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng XU, Kyu-Oh LEE, Junnan ZHAO, Rahul JAIN, Ji Yong PARK, Sai VADLAMANI, Seo Young KIM
  • Publication number: 20190304661
    Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 3, 2019
    Inventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
  • Publication number: 20190291532
    Abstract: The present invention relates to an air conditioner for a vehicle, which can remarkably improve resistance against an air flow in an air passageway, thereby enhancing efficiency. The air conditioner for a vehicle includes: a case having an air inlet, an air outlet, and an air passageway formed therein; a blower unit for blowing air to the air inlet; and a cooling means and a heating means disposed in the air passageway of the case in an air flow direction in order, wherein the air outlet of the case includes a floor outlet and vent outlets, the floor outlet and the vent outlets are arranged below the heating means in a height direction, and the floor outlet is arranged within a range of the width of the heating means.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 26, 2019
    Inventors: Yong Ho KIM, Hak Kyu KIM, Sae Dong EOM, Seung Kyu OH
  • Patent number: 10424561
    Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Publication number: 20190277213
    Abstract: A blended fuel injection control method may include a cold-starting determination step in which a controller determines whether a cold-starting condition is satisfied on the basis of output values that can be obtained by a vehicle; a detection step in which the controller detects the content of ethanol in blended fuel of gasoline and ethanol when determining the cold-starting condition is satisfied; and a first injection control step in which the controller controls the blended fuel to be injected selectively in one of a Multi-Point Injection (MPI) mode, an MPI & GDI mode combining MPI and Gasoline Direct Injection (GDI) modes, and a GDI mode in accordance with the content of ethanol in the blended fuel until an engine RPM reaches an early peak RPM in engine-cranking.
    Type: Application
    Filed: November 6, 2018
    Publication date: September 12, 2019
    Applicants: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Young Kyu Oh
  • Patent number: 10384431
    Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Ji Yong Park, Sri Chaitra J. Chavali, Siddharth K. Alur, Kyu Oh Lee
  • Patent number: 10376480
    Abstract: A biguanide derivative compound with N1-N5 substitution, which is represented by Formula 1, or a pharmaceutically acceptable salt thereof, a method of preparing the same, and a pharmaceutical composition containing the same as an active ingredient are provided. The biguanide derivative may exhibit excellent effect on activation of AMPK? and inhibition of cancer cell proliferation in a low dose, compared to conventional drugs, and thus, may be useful to treat diabetes mellitus, obesity, hyperlipidemia, hypercholesterolemia, fatty liver, coronary artery disease, osteoporosis, polycystic ovarian syndrome, metabolic syndrome, cancer, etc.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 13, 2019
    Assignee: ImmunoMet Therapeutics Inc.
    Inventors: Sung Wuk Kim, Sung Soo Jun, Chang Hee Min, Young Woong Kim, Min Seok Kang, Byung Kyu Oh, Se Hwan Park, Yong Eun Kim, Duck Kim, Ji Sun Lee, Ju Hoon Oh