Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

Abstract: Disclosed are a method and an apparatus for calculating similarity of life log data, the method including: producing, by a life log data producing unit, a plurality of life log data on a daily basis, in which at least one estimated activity state is indicated for each predetermined time section, by matching a user's position information per time period and a user's motion state information per time period with an estimated activity table in which the user's estimated activity states are defined in advance; converting, by a modified life log data producing unit, the plurality of life logs data into a plurality of modified life log data which is indicated for each merged time section made by merging a preset number of continuous time sections; and calculating, by a similarity calculating unit, life log similarity among the plurality of modified life log data by comparing the plurality of modified life log data for each merged time section.

Abstract: A wafer test machine is disclosed. The wafer test machine comprises a main body having a chamber defined therein, wherein a probe card is disposed at an upper portion of the chamber; a chuck for fixing a wafer in the chamber; a moving unit for moving the chuck in the chamber, thus making a contact between the probe card and the wafer; and a laser cleaning apparatus for cleaning the probe card in the chamber using a laser beam, when the probe card does not contact the wafer.

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

Abstract: A device including a two-dimensional (2D) material includes a substrate including a recess recessed from a main surface of the substrate and extending in a first direction, a 2D material pattern on the substrate and intersecting with the recess of the substrate, a gate structure contacting the 2D material pattern and extending in the first direction along the recess of the substrate, a first electrode contacting a first end of the 2D material pattern, and a second electrode contacting a second end of the 2D material pattern. The 2D material pattern extends in a second direction and includes atomic layers that are parallel to a surface of the substrate.

Abstract: Disclosed are a method and an apparatus for calculating similarity of life log data, the method including: producing, by a life log data producing unit, a plurality of life log data on a daily basis, in which at least one estimated activity state is indicated for each predetermined time section, by matching a user's position information per time period and a user's motion state information per time period with an estimated activity table in which the user's estimated activity states are defined in advance; converting, by a modified life log data producing unit, the plurality of life logs data into a plurality of modified life log data which is indicated for each merged time section made by merging a preset number of continuous time sections; and calculating, by a similarity calculating unit, life log similarity among the plurality of modified life log data by comparing the plurality of modified life log data for each merged time section.

Abstract: A wafer test machine is disclosed. The wafer test machine comprises a main body having a chamber defined therein, wherein a probe card is disposed at an upper portion of the chamber; a chuck for fixing a wafer in the chamber; a moving unit for moving the chuck in the chamber, thus making a contact between the probe card and the wafer; and a laser cleaning apparatus for cleaning the probe card in the chamber using a laser beam, when the probe card does not contact the wafer.

Abstract: Disclosed is an apparatus for removing residues present on the surface of a three-dimensional wafer formed with three-dimensional surface structures to clean the surface of the three-dimensional wafer. The apparatus includes a wafer support for supporting a three-dimensional wafer and a CO2 dry ice spray unit for producing solid CO2 dry ice through adiabatic expansion of liquid CO2 at or near a cleaning nozzle and spraying the solid CO2 dry ice on the surface of the three-dimensional wafer through the cleaning nozzle. The CO2 dry ice spray unit includes a liquid CO2 feeder for supplying, the liquid CO2 to the cleaning nozzle and an accelerated clean air feeder for supplying clean air to the cleaning nozzle.

Abstract: A wafer back surface cleaning apparatus for removing foreign substance on a back surface of a wafer with a pulse-wave laser beam is disclosed. The wafer back surface cleaning apparatus comprises a rotating unit for rotating the wafer in condition that the outer portion of the back surface of the wafer is exposed; and a laser beam irradiating unit for irradiating a pulse-wave laser beam onto the outer portion of the back surface of the wafer, wherein the pulse-wave laser beam irradiated location on the wafer changes depending on the rotation of the wafer.

Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.

Abstract: A method of manufacturing a pattern structure, the method includes sequentially forming a mold layer and a mask layer on a substrate, patterning the mask layer to form a mask having a plurality of first and second holes located at vertices of hexagons that form a honeycomb structure, forming filling layer patterns in the first and second holes, removing the mask, forming a spacer on sidewalls of the filling layer patterns and the spacer has a plurality of third holes at centers of the hexagons, removing the filling layer patterns to form an etching mask including the spacer, and etching the mold layer using the etching mask to form the pattern structure having a plurality of openings located at the vertices and the centers of the hexagons.

Abstract: A semiconductor device having low resistance contact to p-type semiconductor layer of a wide band gap compound and a method for manufacturing the same are provided. The semiconductor device includes a p-type semiconductor layer of a GaN based compound formed on a substrate, a p-type carbon nanotube layer, and a metal contact. The p-type carbon nanotube layer is joined to the p-type semiconductor layer of the GaN based compound, and the metal contact is joined to the p-type carbon nanotube layer.

Abstract: Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically contacts the conductive plug opposite the memory cell filed effect transistor. Titanium nitride also may be used to electrically contact field effect transistors in the peripheral region of the integrated circuit memory device. Titanium nitride can be used as a bit line metal instead of conventional tungsten, and as a conductive plug to contact both p+-type and n+-type source/drain regions in the peripheral region of the memory device. The titanium nitride conductive plugs and bit lines may be formed simultaneously.

Abstract: A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a capacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

Abstract: Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically contacts the conductive plug opposite the memory cell filed effect transistor. Titanium nitride also may be used to electrically contact field effect transistors in the peripheral region of the integrated circuit memory device. Titanium nitride can be used as a bit line metal instead of conventional tungsten, and as a conductive plug to contact both p+-type and n+-type source/drain regions in the peripheral region of the memory device. The titanium nitride conductive plugs and bit lines may be formed simultaneously.

Abstract: Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically contacts the conductive plug opposite the memory cell filed effect transistor. Titanium nitride also may be used to electrically contact field effect transistors in the peripheral region of the integrated circuit memory device. Titanium nitride can be used as a bit line metal instead of conventional tungsten, and as a conductive plug to contact both p+-type and n+-type source/drain regions in the peripheral region of the memory device. The titanium nitride conductive plugs and bit lines may be formed simultaneously.

Abstract: According to the present invention, a conductive pad for a self-aligned direct contact and a self-aligned buried contact is formed of a first pad and a second pad, in twice, wherein the self-aligned direct contact and the self-aligned buried contact connect respectively a bit line/storage electrode to a semiconductor substrate. The first pad and the second pad are formed by combining a reverse active type self-aligned contact (RAT-SAC), a contact type self-aligned contact (CT-SAC), and an epitaxial growth processes. Thus, it is prevented that a shoulder portion of a gate electrode is overetched to create electrical short of pad to gate, a size of a pad is limited to a spacing between gate electrodes, a pad and a semiconductor substrate are not electrically connected each other (not-open), and electrical connection is created by lack of margin between BCs, in case of using only one process selected from a group consisting of the RAT-SAC process, the CT-SAC process, and the epitaxial growth processes.

Abstract: A semiconductor memory device and a fabricating method therefor are disclosed. The semiconductor memory device includes a peripheral region and a core region containing a transistor with at least a p+ impurity region. An inter-layer insulating layer is formed on an entire surface of a semiconductor substrate. Then the insulating layer is etched by using a contact forming mask until the surface of the p+ impurity region of the core region is exposed, so as to form contact holes. The contact holes are then filled with a metal to form contacts so as to be electrically connected to the semiconductor substrate. The present invention solves the conventional problem that the contact plug reacts with the impurity ions of the p+ impurity region during the heat treatment, thereby increasing the contact resistance.

Abstract: A novel method for fabricating a semiconductor memory device wherein the interconnection wiring line in a core/peripheral region is formed before bit line in a cell array region formation, thereby preventing damaging of the interconnection wiring line caused during forming the bit line and improving the process margin in the core/peripheral region.

Abstract: An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof.