Abstract: A method of forming self-aligned contact holes of a semiconductor device presents bridging from occurring between contacts formed in the holes. First, gate electrode structures are formed on a semiconductor substrate. Next, an interlayer insulating film is formed over the gate electrode structures. The interlayer insulating film is formed by forming a first oxide layer of a reflowable material over the semiconductor substrate and gate electrode structures, planarization etching the first oxide layer until the upper portions of the gate electrode structures are uncovered, and then forming a second oxide layer on the planarized upper surface of the first oxide layer. The second oxide layer is selected to have a wet etch rate that is lower than that of the first oxide layer. Then, the insulating film is etched to form a contact hole between gate electrode structures.

Abstract: A DRAM cell is formed by forming a capped gate line on a substrate, including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line. Spaced apart source/drain regions are formed in the substrate on opposite sides of the gate line. A dielectric region is formed covering the capped electrode. A storage electrode plug is formed extending from a surface of the dielectric region through the dielectric region and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions. A channel electrode is formed extending from the surface of the dielectric region through the dielectric region and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions.

Abstract: An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof.

Abstract: A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a compacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

Abstract: A DRAM cell is formed by forming a capped gate line on a substrate, including a gate line insulation layer on the substrate, a gate line on the gate line insulation layer and a gate line cap covering top and sidewall portions of the gate line. Spaced apart source/drain regions are formed in the substrate on opposite sides of the gate line. A dielectric region is formed covering the capped electrode. A storage electrode plug is formed extending from a surface of the dielectric region through the dielectric region and along a first sidewall portion of the gate line cap to contact a first of the source/drain regions. A channel electrode is formed extending from the surface of the dielectric region through the dielectric region and along a second sidewall portion of the gate line cap to contact a second of the source/drain regions.

Abstract: A capacitor structure includes a substrate and an insulating layer on the substrate. The insulating layer has a contact hole therethrough extending from a surface of the substrate to a surface of the insulating layer opposite the substrate. A metal plug is provided in the contact hole, and a storage electrode is provided on the insulating layer in electrical contact with the metal plug. Accordingly, the storage electrode is electrically connected to the substrate through the metal plug. In particular, the metal plug preferably comprises a metal such as tungsten having a high melting point. Related methods are also disclosed.

Abstract: A cell transistor for a dynamic random access memory cell (DRAM) is formed on a substrate, including a capped gate line formed on the substrate, spaced apart source/drain regions formed in the substrate disposed on opposite sides of the capped gate line, a capped channel line overlying and separated from the gate line by an intervening dielectric region and contacting a first of the source/drain regions through the intervening dielectric region, and a second dielectric region covering the capped channel line. To form a buried contact, the transistor is etched with an etchant which etches the intervening dielectric region and the second dielectric region at a first rate and gate line and channel line caps covering the gate and channel lines at a second rate, the first rate being greater than the second rate, for an etching time sufficient to expose a second of the source/drain regions while leaving the gate line and the channel line covered.

Abstract: A semiconductor device is fabricated having contact holes formed in an interlayer insulator and on impurity diffusion regions positioned on either side of an isolator, The contact holes are arranged so as not to be disposed along a shortest line path across the isolator. This arrangement isolating interval and provides a structure which can realize higher packing density and improved reliability.

Abstract: A capacitor of a semiconductor device has a plate electrode which process margin and a method of manufacturing same are disclosed. The plate electrode has a planarized surface and borders a source region. A recessed field oxide layer defining an active region is formed on a semiconductor substrate. Then, an insulating pattern for self-aligning an electrode is formed on the active region. The insulating pattern has a step with respect to the field oxide layer. Thereafter, a trench is formed in the semiconductor substrate by partially removing the field oxide layer, the insulating pattern and a surface portion of the semiconductor substrate. A conductive material is deposited on the semiconductor substrate having the trench and the insulating pattern to form a conductive layer filling the trench. Then, the conductive layer is polished until the insulating pattern is exposed, to thereby obtain an electrode having a planarized surface.

Abstract: This invention relates to a semiconductor memory device having a cell array and a peripheral circuit and the fabrication method thereof. A semiconductor memory device and the fabrication method are provided wherein source and drain impurity diffusion regions of transistors constituting the cell array have an impurity concentration lower than that of source and drain impurity diffusion regions of transistors constituting the peripheral circuit Thus, the junction's breakdown voltage characteristic of the transistor in the cell array is improved, and the data inverting phenomenon and refresh characteristic deterioration problem due to the leakage current of the transistor in the peripheral circuit area are both solved.

Abstract: The semiconductor memory device with a stacked capacitor is disclosed. When the mis-align is generated in forming contact region 42 for contact between the storage electrode of the stacked capacitor and the source region 34, the ion-implantation process, with the same conductive type as that of the source region, is carried out, to form the another source region 48 under the bottom surface of the contact region 42, wherein the polysilicon layer on the substrate is used as the mask. The successive ion-implantation provides the diffusion region 58 capable of wholly surrounding the another source region 48, wherein the diffusion region 58 contains higher concentration than that of the substrate and simultaneously lower than that of the source region, with the same conductive type as that of substrate.