Patents by Inventor Kyu S. Min

Kyu S. Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7795607
    Abstract: An apparatus comprising a substrate, an electrode coupled to the substrate, a modifiable layer coupled to the electrode, and a current focusing layer coupled to the modifiable layer. The current focusing layer comprises a conductive region and an insulating region. A method comprising forming a modifiable layer on an electrode and forming a current focusing layer on the modifiable layer.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Kyu S. Min, Nathan R Franklin
  • Patent number: 7763511
    Abstract: Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 27, 2010
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Kyu S. Min, Wilman Tsai
  • Publication number: 20100176432
    Abstract: Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.
    Type: Application
    Filed: January 9, 2009
    Publication date: July 15, 2010
    Inventors: D.V. Nirmal Ramaswamy, Noel Rocklein, Kyu S. Min
  • Patent number: 7750433
    Abstract: Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventors: Kyu S. Min, Nathan R. Franklin
  • Publication number: 20090273016
    Abstract: Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.
    Type: Application
    Filed: May 5, 2008
    Publication date: November 5, 2009
    Inventors: Prashant Majhi, Kyu S. Min, Wilman Tsai
  • Patent number: 7585564
    Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: September 8, 2009
    Assignee: Nanosys, Inc.
    Inventors: Jeffery A. Whiteford, Mihai Buretea, William P. Freeman, Andreas Meisel, Kyu S. Min, J. Wallace Parce, Erik Scher
  • Publication number: 20090146126
    Abstract: Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.
    Type: Application
    Filed: February 12, 2009
    Publication date: June 11, 2009
    Inventors: Kyu S. Min, Nathan R. Franklin
  • Publication number: 20090097320
    Abstract: Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
    Type: Application
    Filed: October 12, 2007
    Publication date: April 16, 2009
    Inventors: Kyu S. Min, Rhett T. Brewer, Tejas Krishnamohan, Thomas M. Graettinger, D. V. Ramaswamy, Ronald A. Weimer, Arup Bhattacharyya
  • Patent number: 7498655
    Abstract: Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: March 3, 2009
    Assignee: Intel Corporation
    Inventors: Kyu S. Min, Nathan R. Franklin
  • Publication number: 20080237691
    Abstract: A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventor: Kyu S. Min
  • Publication number: 20080237683
    Abstract: Methods and structures are described for reducing a gate leakage current and increasing gate coupling ratio in a semiconductor device. In some embodiments, nitride layers are used to limit the oxidation of adjacent silicon gate regions due to oxygen in an intermediate insulator. In various embodiments, the intermediate insulator includes a high-? dielectric material. Apparatus according to embodiments of the invention are also disclosed.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Kyu S. Min, Thomas M. Graettinger
  • Publication number: 20080157171
    Abstract: Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Prashant Majhi, Kyu S. Min, Wilman Tsai
  • Publication number: 20080078982
    Abstract: An apparatus comprising a substrate, an electrode coupled to the substrate, a modifiable layer coupled to the electrode, and a current focusing layer coupled to the modifiable layer. The current focusing layer comprises a conductive region and an insulating region. A method comprising forming a modifiable layer on an electrode and forming a current focusing layer on the modifiable layer.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Kyu S. Min, Nathan R. Franklin
  • Patent number: 7267875
    Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: September 11, 2007
    Assignee: Nanosys, Inc.
    Inventors: Jeffery A. Whiteford, Mihai Buretea, William P. Freeman, Andreas Meisel, Kyu S. Min, J. Wallace Parce, Erik Scher
  • Patent number: 7223701
    Abstract: During microelectronic processing of a substrate, a gap on the substrate surface may be filled with a material by alternating deposition and etch processes while the substrate remains in the same process chamber. Alternating deposition and etch processes allows the gap to be completely filled absent a void.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Kyu S. Min, Oleh P. Karpenko
  • Publication number: 20040048485
    Abstract: During microelectronic processing of a substrate, a gap on the substrate surface may be filled with a material by alternating deposition and etch processes while the substrate remains in the same process chamber. Alternating deposition and etch processes allows the gap to be completely filled absent a void.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Inventors: Kyu S. Min, Oleh P. Karpenko