Abstract: A high frequency device includes: a capping layer formed on an epitaxial structure; source and drain electrodes formed on the capping layer; a multilayer insulating pattern formed on entire surfaces of the source and drain electrodes and the capping layer in a step shape; a T-shaped gate passing through the multilayer insulating pattern and the capping layer to be in contact with the epitaxial structure; and a passivation layer formed along entire surfaces of the T-shaped gate and the multilayer insulating pattern.

Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded.

Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract: Disclosed is a three-dimensional (3D) mesh compression apparatus and method. The 3D mesh compression apparatus may generate a base mesh through a mesh simplification, may separately compress the base mesh and vertices eliminated by the simplification, and may compress 3D mesh data based on the covariance matrix.

Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced.

Abstract: Disclosed is a three-dimensional (3D) mesh compression apparatus and method. The 3D mesh compression apparatus may generate a base mesh through a mesh simplification, may separately compress the base mesh and vertices eliminated by the simplification, may construct a covariance matrix based on a topological distance between the eliminated vertices, and may compress 3D mesh data based on the covariance matrix.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

Abstract: Disclosed is a method and apparatus for encoding a three-dimensional (3D) mesh. The method for encoding the 3D mesh includes determining a priority of a gate configuring a 3D mesh corresponding to a 3D object, removing vertices configuring the 3D mesh using the determined priority of the gate, and simplifying the 3D mesh.

Abstract: A mask assembly includes a frame with an opening, at least one support stick in the frame and extending in a first direction to traverse the opening of the frame, the support stick including a communication pattern above the opening of the frame, and a mask positioned on the frame and the at least one support stick, the mask extending in a second direction perpendicular to the first direction to traverse the opening of the frame, and the mask being exposed to the opening of the frame through the communication pattern.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

Abstract: Provided are a transistor of a semiconductor device and a method of fabricating the same.

Abstract: A data processing apparatus and method. A vertex grouping unit of the data processing apparatus may group, into at least one group, a plurality of vertices included in a three-dimensional (3D) object desired to be compressed. A prediction mode determination unit may determine a prediction mode for compressing a vertex position with respect to each of the at least one group. A coder may code a prediction error vector and an identification (ID) index of the prediction mode determined with respect to each of the at least one group.

Abstract: A mask assembly includes a frame with an opening, at least one support stick in the frame and extending in a first direction to traverse the opening of the frame, the support stick including a communication pattern above the opening of the frame, and a mask positioned on the frame and the at least one support stick, the mask extending in a second direction perpendicular to the first direction to traverse the opening of the frame, and the mask being exposed to the opening of the frame through the communication pattern.

Abstract: Disclosed is a method of manufacturing a field effect type compound semiconductor device in which leakage current of a device is decreased and breakdown voltage is enhanced.

Abstract: Provided are a toner and a method of preparing the same. The toner includes a binder resin, a coloring agent, and at least one additive, and a storage modulus curve of the toner with respect to temperature has multiple inflection points. The toner may be used in an electrophotographic image forming apparatus.

Abstract: Disclosed are a GaN (gallium nitride) compound power semiconductor device and a manufacturing method thereof. The gallium nitride compound power semiconductor device includes: a gallium nitride compound element formed by being grown on a wafer; a contact pad including a source, a drain, and a gate connecting with the gallium nitride compound element; a module substrate to which the nitride gallium compound element is flip-chip bonded; a bonding pad formed on the module substrate; and a bump formed on the bonding pad of the module substrate so that the contact pad and the bonding pad are flip-chip bonded.