Abstract: A semiconductor device having a line-type active region and a method for manufacturing the same are disclosed. The semiconductor device includes an active region configured in a successive line type, at least one active gate having a first width and crossing the active region, and an isolation gate having a second width different from the first width and being formed between the active gates. The isolation gate's width and the active gate's width are different from each other to guarantee a large storage node contact region, resulting in increased device operation characteristics (write characteristics).

Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.

Abstract: Disclosed are a fixing structure of insulation panels and a prefabricated refrigerator with the same. The fixing structure of insulation panels includes a recess recessed on one surface of a first insulation panel having an insulation portion inside a casing, and a protrusion formed to be inserted into the recess, on one surface of a second insulation panel having an insulation portion inside a casing, wherein the insulation portions of nonmetal material are exposed to a bottom of the recess and a front end of the protrusion so as to shield a transmission path of heat flowed along a casing contact surface of the insulation panels, thereby improving insulation efficiency.

Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.

Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.

Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.

Abstract: A vacuum insulation panel and an insulation structure of a refrigerator applying the same are disclosed. The vacuum insulation panel comprises: a sealing cover (120) having an outermost layer exposed to the outside, a gas shielding layer stacked on the bottom surface of the outermost layer and formed of a thin metal sheet and a metal deposition film, and a heating-fusion bonding layer stacked on the bottom surface of the gas shielding layer and formed of an octane-base material; a core material (110) sealed by the sealing cover (120) in contact with the heating-fusion bonding layer, and provided with an extended insulation portion (130) some parts of which are extended between the bonding portions formed at the sealing cover (120); and a gas permeation preventing layer (125) formed on the sealing cover (120), so that can prevent an external air or moisture from penetrating into a vacuum insulation panel.

Abstract: A method for manufacturing a semiconductor apparatus includes forming a contact pad layer over a substrate in an active region; patterning the contact pad layer and the substrate to form a first trench, the first trench defining a contact pad pattern; etching the substrate to form a second trench that extends vertically from the first trench; forming a gate insulating pattern over the substrate in the second trench; and forming a buried gate in the second trench.

Abstract: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.

Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.

Abstract: Provided are a decoration panel and a home appliance with the decoration panel. The decoration panel includes a transparent green glass defining an outer appearance and a decoration film adhered to the green glass to realize a color and pattern seen through the green glass to the outside. The decoration film includes a print layer on which the color and pattern expressed to the outside are printed using a gravure printing process and a reflective layer in which a printing ink containing a white inorganic pigment for improving a color reflectance is printed using the gravure printing process to conceal a green color of the green glass, the reflective layer being disposed on a back surface of the print layer. Thus, an outer appearance of the home appliance may be improved.

Abstract: A phase change memory device includes a semiconductor substrate active region, a plurality of first conductivity type silicon pillars, and a plurality of second conductivity type silicon patterns. The plurality of first conductivity type silicon pillars is formed on the semiconductor active region such that each first conductivity type silicon pillar is provided for two adjoining cells. The plurality of second conductivity type silicon patterns is formed on the plurality of first conductivity type silicon pillars such that two second conductivity type silicon patterns are formed on opposite sidewalls of each first conductivity type silicon pillars. Two adjoining cells together share only one first conductivity type silicon pillar and each adjoining cell is connected to only one second conductivity type silicon pattern which constitutes a PN diode which serves as a single switching element for each corresponding cell.

Abstract: Disclosed are a vacuum insulation panel and an insulation structure of a refrigerator using the same. The vacuum insulation panel comprises a core material formed by gather glass fiber, a getter having a container to receive an absorbent having quicklime of 90 wt % or greater as a main component, and a sealing cover formed to surround the core material and the getter. The core material can be formed at low cost in such a manner that glass fiber is tangled and gathered by penetrating glass wool having glass fiber using a needle. Since the getter is made of quicklime that can first remove water corresponding to a main component of the absorbent, the getter can be manufactured at low cost and has improved insulation efficiency.

Abstract: A semiconductor device includes a silicon substrate; a device isolation structure formed in the silicon substrate to delimit an active region which has a pair of gate forming areas, a drain forming area between the gate forming areas, and source forming areas outside the gate forming areas; an asymmetric bulb-type recess gate formed in each gate forming area of the active region and having the shape of a bulb on the lower end portion of the sidewall thereof facing the source forming area; and source and drain areas respectively formed on the surface of the substrate on both sides of the asymmetric bulb-type recess gate.

Abstract: The present invention relates to an external film for an electric home appliance and a home appliance using the same, there are advantages in that strength of the external film is reinforced and the product is reduced in weight while having the feeling of texture of metal materials, as a PET layer or a PVC layer is provided at upper and lower surfaces of a metal layer such as an A1 layer.

Abstract: The reinforcing component for a refrigerator, which is formed by mixing a base material as a synthetic resin material and a supplement component formed by arranging reinforcing fibers according to a pultrusion method, and combined with one or more portions of on one portion of an inner side of an outer case of the refrigerator to contact with foam, a corner of the bottom of the refrigerator or in a mechanic chamber of the refrigerator, an outer plate or an inner plate of a door of the refrigerator, and the interior of a side wall forming an inner space of the refrigerator can reduce the weight of the refrigerator while maintaining the strength.

Abstract: A phase change memory device includes a semiconductor substrate active region, a plurality of first conductivity type silicon pillars, and a plurality of second conductivity type silicon patterns. The plurality of first conductivity type silicon pillars is formed on the semiconductor active region such that each first conductivity type silicon pillar is provided for two adjoining cells. The plurality of second conductivity type silicon patterns is formed on the plurality of first conductivity type silicon pillars such that two second conductivity type silicon patterns are formed on opposite sidewalls of each first conductivity type silicon pillars. Two adjoining cells together share only one first conductivity type silicon pillar and each adjoining cell is connected to only one second conductivity type silicon pattern which constitutes a PN diode which serves as a single switching element for each corresponding cell.

Abstract: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below both ends of the floating gate; a ferroelectric substance interposed between the silicon substrate and the floating gate inside the tunnel oxide film; a diffusion barrier film enclosing the ferroelectric substance; a control gate formed on the substrate including the floating gate; a gate oxide film formed below the control gate; spacers formed on both lateral walls of the laminated floating gate and control gate including the tunnel oxide film and gate oxide film, respectively; and source/drain regions formed within the substrate surfaces on both sides of the control gate including the spacers, respectively.

Abstract: A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.

Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.