Abstract: A color toner composition for developing latent electrostatic images includes nanopowder-coated toner particles, the powder-coated toner particles being characterized in that each comprises a core toner particle having a volume average diameter, Dp, and the core toner particles have affixed to their surfaces a plurality of discrete colorant powder particles having a volume average diameter, dp, wherein the ratio of Dp/dp is at least about 5 and the weight fraction of colorant powder particles is at least about 0.01 based on the combined weight of core toner particles and colorant powder particles. Preferably, the weight fraction of colorant powder particles is from about 0.3 to about 3 times the product, (?p/?r) (d/r) (1+d/r)2, where ?p is the density of the colorant powder particles, ?r the density of the core resin particles, d, the volumetric mean diameter of the colorant powder particles and r the volumetric mean radius of the toner core resin particles.

Abstract: A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a reference voltage or comparing the cell resistance with a set state cell resistance. The duration of the set pulse is controlled in response to the detected state of the memory element. The result of the approach of the invention is the significant reduction in PRAM programming errors, such as those caused by a constant-duration set pulse, as well as reduction in programming time duration and power consumption.

Abstract: A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a reference voltage or comparing the cell resistance with a set state cell resistance. The duration of the set pulse is controlled in response to the detected state of the memory element. The result of the approach of the invention is the significant reduction in PRAM programming errors, such as those caused by a constant-duration set pulse, as well as reduction in programming time duration and power consumption.

Abstract: A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a reference voltage or comparing the cell resistance with a set state cell resistance. The duration of the set pulse is controlled in response to the detected state of the memory element. The result of the approach of the invention is the significant reduction in PRAM programming errors, such as those caused by a constant-duration set pulse, as well as reduction in programming time duration and power consumption.

Abstract: A circuit and method for programming phase-change memory devices, such as chalcogenide memory (PRAM), are described. The invention is directed to an approach to programming PRAM elements from a reset state to a set state or from a set state to the set state. The invention provides a novel and nonobvious PRAM device and method in which a set pulse duration time is controlled by monitoring the state of the memory element during programming such as by comparing the voltage of a bit line with a reference voltage or comparing the cell resistance with a set state cell resistance. The duration of the set pulse is controlled in response to the detected state of the memory element. The result of the approach of the invention is the significant reduction in PRAM programming errors, such as those caused by a constant-duration set pulse, as well as reduction in programming time duration and power consumption.

Abstract: A vertical rotation shaft assembly for a swing-arm type door having a door plane and a cylinder for actuating the door includes an upper rotational shaft extended from the cylinder as a piston rod and a lower rotational shaft inserted into an edge of the door plane, the lower rotational shaft being coaxially arranged with the upper rotational shaft.

Abstract: A melody producing candle in which an Integrated Circuit (IC) placed within the candle is activated upon kindling of the wick to produce music. The candle stops playing music once the flame is put out. The invention is provided with a light reflector which allows adjustment of sensitivity of the candle to light.